Veloce Emulation Systems
The Veloce verification system reduces project schedules and cost through high-performance Questa simulation acceleration and in-circuit emulation of complex SoC designs. Veloce achieves these benefits through a unique architecture and best-in-class technologies.
Mentor’s second-generation emulation product, Veloce2, is based on a new, state-of-the-art emulation SoC and has scalable hardware configurations for verifying designs from 16 million to 2 billion gates. Complementary software and application solutions offer a complete Veloce2 verification environment.
- Acceleration of block, module, and full SoC regression test runs is many orders of magnitude faster than simulation
- Comprehensive, simulation-like debug environment for ease-of-use
- Hardware platform for software development and debug enables pre-silicon testing
- Full system integration using real-world stimulus and software for testbenches before first silicon is available
- VirtuaLAB solutions to create a “virtual lab” environment of software-only applications and standards-based protocols for the verification of SoCs, without the need for external hardware connections to Veloce
- Accelerated regression tests speed up post-silicon validation before committing changes to silicon
- High-speed platform, highly tuned for hardware-software concurrent engineering
- Connects to multiple software development environments for greater flexibility in verification and debug
- Fast, integrated compile and place-and-route software delivers consistent results and high-quality route to begin runtime testing
- Eliminates most silicon respins by running billions of cycles to find hard-to-find bugs missed by traditional methods
- Capable of handling many interfaces, driving stimulus simultaneously from live and virtual devices
- Architected to accelerate advanced verification environments based upon UVM, OVM, VMM, and TLM
- Best vehicle for low power verification using real-world scenarios
- Simulation-like use model for assertion and coverage based verification
- Standard queuing support for optimal utilization of emulation resources among various teams and sites
New-generation, high-performance, high-capacity hardware-assisted solution for verifying embedded systems and SoC designs.
Co-modeling software application for accelerating modern testbench environments up to 10,000 times over software simulators.
Physical, specialized devices cabled to Veloce2 for the modeling of standards-based protocols and the rapid construction of complete, high-performance SoC verification environments.
Flexible, pre-configured software models for protocol-specific host and peripheral interfaces create a “virtual lab” environment for high-performance verification of SoC designs.
Versatile, easy-to-use catalog of VIP for simulation or emulation, easing the transition from simulation to acceleration.
- Software Debug Connections
- Accelerating OVM/UVM
- Assertions-Based Verification
- Codelink Integration
- Vista Integration
Software Debug Connections
Software Debug Connections to Veloce
Software debug connections to emulation have traditionally been handled using hardware-based, JTAG probe connections, as shown.
Because JTAG uses a serial data connection, performance is limited on the emulator.
A new approach is to use parallel connections, as shown in the latest ARM-based tools, called “VSTREAM”, which can improve performance over traditional JTAG by 5–10x. In addition, this solution uses a software, transaction-based interface between the software debug tools and the Veloce2 emulator, greatly improving flexibility and ease-of-use, especially for remote users.
Accelerating OVM/UVM Testbench Environments in Veloce
The methodologies defined in the OVM standard, which have now progressed to UVM standards, are supported using the Veloce2 emulation environment. Mentor’s unique TestBench-XPress (TBX) technology delivers the same functionality achievable in simulation, but at 1000s of times faster performance. Additionally, it greatly increases verification productivity by using the same testbench for simulation and Veloce2 accelerated verification.
Assertions-Based Verification Using Veloce
Veloce2 delivers a comprehensive, standards-based ABV solution, offering the choice of SVA, PSL, OVL, and QVL solutions. Assertion checkers and monitors ease the use of ABV methods. These checkers cover a wide range of design properties and are optimized for emulation users. Since the same ABV methods can be used in simulation and emulation, the transition from simulation to emulation is easier. Veloce2 generates assertion and coverage reports in exactly the same format as simulators.
Mentor offers a consistent flow for assertions across a wide range of tools, including emulation.
- Same design, assertions, and testbench used for each engine
- Collect coverage across simulation, emulation, and formal analysis
- Maximize efficient use of verification tools
The integration of Veloce2 and Codelink provides a high-speed, software-driven, hardware verification environment for debugging SoCs that use embedded processors.
During a Veloce2 emulation run, Codelink's advanced tracing technology automatically captures all of the important activity inside the design's processors, enabling the verification engineer to "playback" the emulation at a later time; thus offloading the Veloce2 emulator to allow other regression runs to be performed while debugging the results of a previous run.
Innovative debug features include fast forward, rewind, pause, single step, and even the equivalent of zoom-and-pan to make the debug session appear just like an interactive session. Synchronization between the software code and hardware emulation is maintained and easily viewed, including emulation waveforms, processor states, source code, internal memory, registers, stacks, and output.
Allowing tens or even hundreds of software engineers to access the emulated design data during software debug results in a huge productivity boost and creates a large ROI in Veloce2 resources.
System Level — Vista Virtual Prototype
Vista is an integrated TLM 2.0-based solution for architectural design exploration, verification, and virtual prototyping for designing, optimizing, and validating SoC hardware and software. As the hardware architecture becomes more refined, where blocks and sub-systems can be created in RTL, there is a significant value in being able to run hybrid verifications of these RTL modules with software and other hardware blocks that are still represented as higher-level descriptions—the latter being the “Vista Virtual Prototype.”
Veloce2 can play a significant role in boosting the productivity of these hybrid verifications by accelerating the RTL runtimes and using the Vista virtual prototype platform as a virtual target for the DUT running in Veloce2.
- Hybrid of Vista base platform and accelerated JPEG RTL on Veloce2
- RTL runs on Veloce2 at MHz speeds
- Software runs on Multi-core Cortex A9 TLM model in the 100s MIPS range
- Catapult generated JPEG RTL accelerated on Veloce2
- Instantiating interface compatible SCE-MI based Veloce2 transactors
- JPEG RTL appears as Vista TLM
- Vista platform is the virtual target for Veloce2 DUT
- HW/SW co-debug on Vista/Veloce2-TBX