TestBench XPress

TBX establishes a SCE-MI compliant, transaction-level communications link between testbenches running on a host system and an SoC modeled in Veloce2. By accelerating both block-level and full-SoC regression tests, Veloce2 and TBX significantly reduce development schedule risks while leveraging transaction models used during simulation.

In co-modeling, reusable testbenches are interfaced to synthesizable transactors collocated with the DUT in Veloce2. These “accelerated” transactors convert high-level transactions to signal-level stimuli to drive the DUT.

SystemVerilog DPI exported and imported tasks are the primary transaction modeling constructs of TBX. This makes it straightforward to use Mentor supplied transactors or develop your own. TBX automatically generates a direct communication interface between the C/C++ or SystemC environment on a host and the SoC DUT in the Veloce2 emulator. With SystemVerilog testbenches, TBX executes the testbenches using the Questa simulator on the host PC.