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Veloce2

Veloce2 accelerates block and full SoC RTL simulations during all phases of the design process. Veloce2 enables pre-silicon testing and debug at hardware speeds, using real-world data, while both hardware and software designs are still fluid.

Veloce Diagram

Key benefits

  • Improves end product quality by increasing the total verification cycles on the design before committing to silicon prototypes
  • Reduces silicon spins due to functional problems by enabling full-system integration testing before first silicon
  • Moves software off the project’s critical path by allowing debugging on emulated hardware early in the design process
  • Improves ROI by becoming the verification hub for simulation and emulation of SoC designs

The Veloce2 product family includes:

  • Scalable verification platforms with capacities from 16 million to 2 billion gates
  • Common configuration and debug software across the Veloce family
  • Simulator-like debug environment
  • 100% internal DUT visibility
  • Network accessible, multi-user systems

Veloce2 hardware and software solutions allow design teams to quickly create reconfigurable hardware representations of new SoC designs and leverage verification investments across the project. This reduces the risk of design flaws in pre-silicon testing by verifying the SoCs compliancy and interoperability with industry-standard protocols, thus reducing overall project schedules and costs.

Comprehensive verification environment

Mentor’s software and application solutions enable a comprehensive verification environment for IP, chip, and system level verification.
  • TestBench XPress software enables transaction-based, co-emulation verification with support for untimed C/C++, SystemC, and SystemVerilog testbenches
  • iSolve solutions, delivered as physical hardware-based products, provide application and protocol-based solutions for several vertical market areas; including video/audio, networking, wireless, embedded software, and storage
  • Verification IP delivers higher levels of productivity for simulation and for acceleration of IP and SoC verification
  • Veloce VirtuaLAB devices are software solutions that create a “virtual lab” environment for SoC verification and provide greater flexibility and visibility over a target protocol in applications such as video/audio, storage, and networking as well as industry-standard bus protocols
  • Low power verification
  • Advanced methodology support of UVM, OVM, VMM, TLM, etc.
  • Assertion-based verification support in Veloce2 provides the same advanced capabilities as simulation for QVL, SVA, OVL, and PSL
  • Connections to software development tools through physical and virtual JTAG solutions
  • Integrations with Electronic System Level (ESL) tools using Vista with Veloce2
  • Highly productive, software-driven hardware verification using Codelink with Veloce2
 
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