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Veloce Transactors

Veloce Transactors apply the appropriate stimulus for the SoC executing in Veloce2, delivering a scalable verification solution for popular protocols and standard interfaces that can be used for RTL, TLM, and system-level verification.

Veloce Transactors are easy and convenient to use, reducing overall testbench development time and completing more verification with less effort.

Connected directly to a high-performance emulation environment, Veloce Transactors deliver acceleratable verification IP (VIP) that run up to 10,000 times the speed of pure software simulation, significantly reducing verification times and regression testing for increased productivity.

Veloce Transactor models can be used in various HVL testbench environments, including SystemC and SystemVerilog, and deliver the stimulus generators, monitors, and score boarding capabilities used with the OVM/UVM standards.

 
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