Veloce

The Veloce product family reduces project schedule and cost risk by delivering high performance simulation acceleration and pre-silicon, real world testing using SoC in-circuit emulation.

The Veloce family consists of …

  • Five scalable Veloce verification platforms with capacities from 8 million gates up to 512 million gates
  • Common configuration and debug software
  • Simulator-like debug environment
  • 100% internal DUT visibility
  • Network accessible, multi-user systems

Veloce: Your Complete Verification Solution

Veloce has many software and application solutions to provide a comprehensive verification environment for your designs.

  • Transaction-based, co-emulation verification with the TestBench XPress Software supporting untimed C/C++, System C, and System Verilog test benches
  • HDL Link Software for mixed level, vector-based co-simulation with the Questa simulator and high performance, free-running regression testing
  • iSolve Solutions for complex memory modeling, industry standard bus and communications interfaces, multi-media data streaming and data analysis, embedded processor modeling and software debugging
  • Assertion-based verification supporting 0-In, SVA, OVL, and PSL

Veloce systems and accompanying solutions and software allow design teams to quickly create reconfigurable hardware representations of new SoC designs and leverage verification investments across the project. This reduces overall schedule and costs by:

  • accelerating block and full SoC RTL simulations,
  • allowing re-use of signal level and transaction-based testbenches, and
  • re-using simulation assertion-based test technology.

Veloce Product Family

Veloce
Solo

Veloce
Trio

Veloce
Quattro

Veloce
Grande

Veloce
Maximus

Simulation Acceleration

Emulation Mode
Max Capacity M-gates 16 48 (16/user max.) 128 256 512

Details

Veloce Simulation Acceleration/In-Circuit Emulation Systems

The Veloce product family reduces project schedule and cost risk by delivering high performance simulation acceleration and pre-silicon, real world testing using SoC in-circuit emulation. The Veloce family consists of:

  • Five scalable Veloce verification platforms with capacities from 8 million gates up to 512 million gates
  • Common configuration and debug software
  • Simulator-like debug environment
  • 100% internal DUT visibility
  • Network accessible, multi-user systems

The Veloce Value Proposition

Beyond accelerating your block and full SoC RTL simulations during all phases of your design process, Veloce enables pre-silicon testing and debug at hardware speeds with real-world data, while both hardware and software designs are still fluid. This has the benefit of:

  • Improving end product quality by increasing the total verification cycles on the design before committing to silicon prototypes
  • Reducing silicon spins due to functional problems by enabling full system integration testing before first silicon, and
  • Moving software off the project’s critical path by allowing debugging on emulated hardware early in the design process.

Toolbox

Collateral

  • Veloce-based Simulation Acceleration Veloce-Based Simulation Acceleration speeds up block-level and full SoC regression test runs by 100s to 1000s of times, (1) during block and full SoC RTL development and (2) post-silicon validation by accelerating post-change regression tests.
  • Veloce-based In-circuit Emulation To accommodate the increasing complexity of today’s SoC designs many design teams are moving to high-level design languages, like System Verilog and System C, and transaction-level modeling for test benches to speed up their development and functional verification efforts.
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