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VirtuaLAB

In combination with Veloce2 and the TBX co-modeling technology, VirtuaLAB delivers a fully virtual, block to system level accelerated verification flow for emulation users. VirtuaLAB emulation is the correct approach for pre-silicon verification of SoCs that have multiple chip interfaces connected to peripherals and host devices. By providing virtual devices for these interfaces, VirtuaLAB delivers ease-of-use and greater productivity than in-circuit emulation (ICE), while delivering the same functionality as ICE. This allows the emulator to be moved out of the lab environment and into a datacenter that can be accessed by multiple hardware and software engineers across different locations.

Benefits

VirtuaLAB offers the following key benefits for emulation users:

  • Manage emulation resources from a datacenter. By changing peripheral models from ICE to VirtuaLAB, the emulator can be moved into a datacenter, so it is no longer confined to a single lab and a single user
  • Rapid return on investment by offering flexible, always-on access to emulation for all software, hardware, and integration engineers on all projects at the same time
  • Inherently more reliable than ICE. For hardware engineers, moving the emulator out of the lab and into the datacenter puts an end to downtime caused by cable dislodgement, pin breakage, lack of available pins, or overnight waits for remote lab staff to swap cables between external hardware targets
  • Greater multi-user flexibility than ICE as it can replicate a user’s environment many times over without the need for multiple, expensive testers or other target hardware connected to the emulator, which occupy large amounts of lab space as well
  • Reuse of the same monitors and protocol checkers right through simulation to emulation, delivering better quality products and removing the need to use expensive logic analyzers for debugging protocol issues during ICE
  • Visibility into the target protocol software stack running on the function controller and can be defined without the constraint of a specific access mechanism into dedicated hardware, which would be needed for equivalent ICE solutions

Because the VirtuaLAB flow supports SystemC and SystemVerilog with both Veloce2 and Questa, users can integrate VirtuaLAB solutions into an environment using UVM/OVM for testbench protocol interfaces and verification IP.

By using a TBX co-model link to package a software stack running on a co-model host workstation with communication protocol IP running on Veloce2, users of VirtuaLAB can verify their IP at the device driver level and verify the DUT with realistic software.

 
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