Veloce VirtuaLAB Solutions

In combination with Veloce2 and the TBX co-modeling technology, Mentor Graphics Veloce VirtuaLAB solutions deliver a fully virtual, block-to-system level accelerated verification flow. Virtualization makes emulation more readily available to all design teams and increases the flexibility, visibility, and capacity of emulation environments while increasing verification productivity and design quality.

VirtuaLAB solutions offer the same functionality as traditional In-Circuit (ICE) solutions but without the need for additional cables and hardware units. Thus, VirtuaLAB offers additional advantages.

  • Easier and more flexible remote usage because the solution can be installed with no additional hardware connected to Veloce2
  • Visibility over the target protocol software stack running on the function controller can be defined without the constraint of a specific access mechanism into the dedicated hardware
  • Access to standard buses is readily available for monitors and checkers
  • Greater flexibility for sharing a single Veloce2 resource among multiple design teams because there are no cables to connect and there are fewer partition constraints on the DUT running in the emulator
  • Visibility/traceability over the target protocol function controller core can be defined in terms of simple IP protection for the delivered RTL source code

Because the VirtuaLAB flow supports SystemC and SystemVerilog with both Veloce2 and Questa, users can integrate VirtuaLAB solutions into an environment using OVM/UVM for testbench protocol interfaces and Questa Verification IP.

By using a TBX co-model link to package a software stack running on a co-model host workstation with communication protocol IP running on Veloce2, users of VirtuaLAB can verify their IP at the device driver level and verify the DUT with realistic software.

Datasheets

Toolbox