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- Custom Emulation-on-Chip SoC
- High-performance acceleration and emulation platform
- Up to 1.5 MHz throughput
- Compiles rate of 15M gate per hour
- Simulation-like debug environment
- 100% visibility without recompiling
- Assertion support - SVA, PSL, OVL, O-In Checkerware
- Scalable capacity up to 128M gates in 3 unique footprints
- Multi-user platform
- Handles true asynchronous clock behaviors
Benefits - Efficient platform for both acceleration and emulation
- Single platform for:
- block/sub-chip verification
- Embedded system and SoC validation
- Pre-silicon prototyping
- Software design and validation
- Post-Silicon bring-up and debug
- Increased overall productivity (Compile, Run, Debug)
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