Equivalence Checking
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Equivalence checking provides 100 percent logic verification coverage of your gate level netlists by comparing the new netlist to a golden reference. The reference can be RTL design files that were verified with static and dynamic methods, or a previously verified gate-level netlist. Equivalence checking uses exhaustive mathematical proofs to verify that the candidate is exactly equivalent to the reference. Comparisons can be made across language and structural differences. The process is exceptionally fast due to static formal methods. For the same reason, equivalence checking provides the level of performance needed for fast regression testing. For example, a leader in broadband networking equipment recently ran regressions of a 9.6 million-gate ASIC on a standard 32-bit Linux workstation implemented in a physical design flow. It took about an hour and a half to perform a gate-to-gate, first-to-final netlist verification of the entire system-on-chip implementation. Additional Information:
PRODUCTS
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