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Accelerating Your Verification Schedule with Veloce



Overview of Veloce hardware emulator with emphasis on SW debug, UVM acceleration, and low-power design. Integrated SW/HW debug and UVM testbench acceleration with Questa will be demonstrated.

What You Will Learn

  • Compile flow for mapping RTL designs into Veloce
  • Full visibility design debug features
  • SW/HW debug for multi-core ARM-based designs
  • Accelerating UVM driven verification
  • Virtual peripheral solutions for USB, PCIe, Ethernet, and Multimedia
  • UPF driven low-power design verification

About the Presenters

Presenter Image Vijay Chobisa

Vijay is product marketing manager for Veloce and TBX products. He has been working in emulation/acceleration for last 11 years. Prior to that he did ASIC designs for three years. Vijay has received Bachelor of Engineering (B.S.) in Electronics and Telecommunication from M.B.M. EngineeringCollege Jodhpur, INDIA.

Presenter Image Jim Kenney

Jim Kenney has 30 years of simulation experience including hardware emulation and HW/SW co-simulation. He’s worked as a developer, applications engineer, and is currently the Marketing Director for Mentor’s Emulation Division. He holds a BSEE from Clemson University.

Who Should Attend

  • Functional Verification Engineers
  • Functional Verification Leads and Managers
  • ASIC/SOC project lead
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