Advanced Verification Seminar
Overview
This Advanced Verification Seminar is a two day event.
As functional verification challenges continue to pressure project schedules, the need to increase productivity while efficiently managing against plan continues to grow.
This seminar will focus on the methodology, tools and infrastructure you'll need to enable you to handle those large verification projects headed your way. By architecting Questa and the Open Verification Methodology (OVM) to provide revolutionary productivity and predictability benefits in an evolutionary way, Mentor Graphics is uniquely positioned to help you achieve your goals, both technically and organisationally.
Today's complex verification projects demand you take advantage of advanced techniques like constrained-random stimulus, functional coverage and assertions, and Questa and the OVM give you the jumpstart you need to integrating them into your flow. By integrating our clock-domain crossing (CDC) and formal verification solutions, as well as our Questa Power-Aware solution, a new universe of unparalleled productivity is at your fingertips. When combined with Questa's unique verification management facilities, you now have a way to track every aspect of your verification activities back to your verification plan, analyze your results in a logical way, and know that you've properly addressed every requirement. These verification techniques and methods fully supports VHDL and Verilog at RT Level as well as SystemVerilog and SystemC at higher levels of abstraction.
The second day will introduce the verification capabilities supported in Questa, including Object Oriented Programming, constrained random stimulus, assertions and functional coverage. A look at the technical details behind the OVM will be followed in the afternoon by 2 hands-on workshops covering assertion based verification and verification management using Mentor's Questa verification platform.
Who Should Attend
- Designers
- Verification Engineers
- CAD Team Members
- Technical Managers (Day 1)
What You Will Learn
Day 1: 11 December
will introduce and explain the benefits of the latest functional verification techniques and methodologies.It will highlight how these can be used to help manage a verification process to improve quality and reduce wasted effort.
The use for formal verification will be explored along as will addressing the verification challenges of designs with multiple, asynchronous clock domains.
Techniques to functionally verify low power designs with independent power islands will also be covered.
Day 2: 12 December
will introduce the important elements of the SystemVerilog language relating to verification and explain how these can be applied to VHDL and Verilog RTL designs.The advantages of adopting a structured approach to building verification environments using the Open Verification Methodology (OVM) will then be covered, highlighting the productivity advantages it delivers.
Two hands on workshops will complete the day, covering assertion based verification and verification management using Questa/ModelSim.
@ IMEC - supported by Mentor Graphics
Date: 11 & 12 th of December
Location: IMEC
Addresse: Kapeldreef 75
B-3001 Leuven
Belgium
Tel: +32 (0)16 28.12.11
Fax: +32 (0)16 22.94.00