Advanced FPGA Design - Seminar
In today’s highly competitive marketplace there are few differentiators between competing suppliers’ products except for price, reliability and time-to-market. In many cases the use of FPGAs for substantial parts of the hardware design has helped with the price, partially helped with the reliability, but at the cost of time-to-market. This is not down to the FPGA itself, more down to the basic and frequently outdated techniques used for FPGA design and verification.
Mentor Graphics have concentrated on developing tools which speed up design capture as well as allowing parts of existing designs to be easily reused, accelerating time-to-market.
Ensuring rapid, quantifiable verification as well as easy documentation help achieving your goals –providing you with the confidence that your objectives have been met.
Mentor Graphics solutions fit easily into your existing design flow, leveraging a mix of textual and graphical design entry as well as generating graphics for documentation and debugging purposes.
In this event we will discuss the some of these techniques for advanced design, verification and documentation that we can provide. We will also demonstrate how leveraging these using Mentor Graphics' FPGA tool flow will allow your company to stay ahead of the pack.
What You Will Learn
- The use of Assertions to automatically check for desired and/or undesired functionality
- Automating the verification flow to speed this up and make it repeatable
- Automating the requirements tracking task for documentation (i.e. DO-254, military. space, medical, etc.)
- Automating the documentation task for projects
- Using vendor-independent HDL Synthesis to improve implementation and provide multi FPGA vendor flows
About the Presenter
Jakub Šťastný received the M.S. degree in electrical engineering from the Faculty of Electrical Engineering of the Czech Technical University (FEE CTU), Prague in 2002; Ph.D. degree in theoretical electrotechnic in 2006. He has 10 years of experience in digital ASIC design (low power digital design, digital signal processing); currently he is a Senior IC designer at ASICentrum s.r.o. (he joined the company in 1999).
He was and still is participating in many commercially successful ASIC projects in ASICentrum either as a designer, or team leader. He is also a founder and supervisor of the FPGA Laboratory at the Department of Circuit Theory, Faculty of Electrotechnical Engineering, Czech Technical University in Prague where he also teaches digital system design using Mentor Graphics design tools.
Who Should Attend
- Verification engineers
- Design engineers
- Project managers
- Engineering managers
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