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Advanced FPGA Verification with Questa Seminar



Electro-Source, partnering with Mentor Graphics, Hardent and Xilinx, is proud to present a comprehensive seminar on a revolutionary verification flow for complex FPGAs.

This seminar will focus on three major topics related to improving design verification through process automation. Each topic is a train journey with three stops. We will look at assertions, coverage and UVM Express. The stops will help you get the most out of your tools and methodology. Regardless of whether you ride the train to the last stop or jump off at the first, what you learn will make you better off than before you started the journey.

FGPA's continue to get larger and more complex. Today's FPGA's are where ASIC's were 10 years ago. This means that the days of just writing some code and running to the lab to test it are ending. We must move toward a milestone of "Verification Complete" and FPGA designers need to start thinking about new methods to achieve this goal.

What You Will Learn

  • New Trends in FPGA Verification Methodologies
  • How to reduce debug Time by 50%
  • How to build an effective Testbench Infrastructure
  • The Vivado Design Flow

Who Should Attend

  • FPGA Designers
  • FPGA Verification Engineers
  • FPGA Team Leaders and Managers

About the Presenters

Presenter Image Reg Zatrepalek

After completing his Bachelor of Science, Reg started his career as a hands-on Engineer, followed by a Field Application position at Xilinx. He is currently working as an FPGA Specialist, Trainer and Consultant at Hardent Inc, an authorized training provider for Xilinx. Working with Xilinx for over 15 years has accredited him to share his extensive expertise, training engineers across North America on the latest Xilinx technology. The vast experience accumulated throughout his career is reflected in his professionalism and command of the current tools on the market.

Presenter Image Walter Gude

Walter has over 25 years of experience in ASIC/FPGA design and holds a MS in Electrical Engineering from Washington University in St. Louis. He worked for 6 years doing ASIC design at Tellabs Operations. From there, he went to work for Mentor Consulting where he consulted on various ASIC projects including time spent in Munich Germany and Helsinki Finland. For the last decade, Walter has worked as an Application Engineer supporting Mentor's line of Functional Verification Projects.

Products Covered


  • 09:00 – 09:30 Registration
  • 09:30 – 09:40 Welcome and Introduction
  • 09:40 – 09:55 Why you need a Verification Process
  • 09:55 – 10:10 Three Steps to injecting Automation
  • 10:10 – 10:20 Break
  • 10:20 – 10:50 Reduce debug Time by 50%
  • 10:50 – 11:20 Understand where you are in the Verification Process
  • 11:20 – 12:00 Build an effective Testbench Infrastructure
  • 12:00 – 13:00 Lunch
  • 13:00 – 13:45 The Vivado Design Flows
  • 13:45 – 14:45 Vivado Visualization capabilities
  • 14:45 – 15:15 Xilinx design constraints (XDC) introduction
  • 15:15 – 16:00 Summary, Closing Remarks, Draw
Online Chat