Advanced FPGA Verification Seminar
Electro-Source, partnering with Mentor Graphics, is proud to present a comprehensive seminar on a revolutionary verification flow for complex FPGAs.
This seminar will focus on three major topics related to improving design verification through process automation. Each topic is a train journey with three stops. We will look at assertions, coverage and UVM Express. The stops will help you get the most out of your tools and methodology. Regardless of whether you ride the train to the last stop or jump off at the first, the learning will make you better-off than before you started the journey.
FGPA's continue to get larger and more complex. Today's FPGA's are where ASIC's were 10 years ago. This means that the days of just writing some code and running to the lab to test it are ending. We must move toward a milestone of "Verification Complete" and FPGA designers need to start thinking about new methods to achieve this goal.
What You Will Learn
- New Trend in FPGA Verification Methodologies
- How to reduce debug Time by 50%
- Build an effective Testbench Infrastructure
About the Presenter
Joe Rodriguez is a FPGA Market Development for Design Verification Technology (DVT) division at Mentor Graphics. Prior to this role Joe spent 2 years as Technical Marketing Manager for the Emulation Division (MED) at Mentor Graphics. Joe was also the Technical Marketing Manager in DVT at Mentor Graphics for 12 years. A result of this Joe has been involved in the definition and creation of many aspects of the Mentor Graphics verification solutions. Solutions like power aware simulation, debug and performance flows, including US patents for simulation event reduction.
Prior to Mentor Graphics, Joe spent 5 years as a field application engineer for Quickturn Design Systems successfully deploying many large FGPA based emulation projects. Joe also spent 6 years at Logic Automation as a Modeling Engineer and Support Manager. Joe has 7 years experience as a diagnostic engineer at Floating Point System and holds a Bachelor of Science in electrical engineering.
Who Should Attend
- FPGA Designer
- FPGA Verification Engineer
- FPGA Team leader and Manager
08:30 - 09:00 Registration
09:00 - 09:10 Welcome and Introduction
09:10 - 09:20 Why do you need a Verification Process
09:20 - 09:30 Three Steps to injecting Automation
09:30 - 10:00 Reduce debug Time by 50%
10:00 - 10:10 Break
10:10 - 10:40 Understand where you are in the Verification Process
10:40 - 11:15 Build an effective Testbench Infrastructure
11:15 - 12:00 Summary, Closing Remarks
12:00 - 13:00 Lunch
Injecting Automation into Verification – Improved Throughput
Improving productivity has many forms, simulation performance, debug effectiveness, even writing test scenarios. We will highlight high value techniques for improving throughput.
Injecting Automation into Verification - Assertions
What we will show in this webinar is how we can leverage Assertions, including the pre-defined, pre-tested OVL libraries, to automate the verification process further. What we will also show is the way...
Injecting Automation into Verification – Code Coverage
This webinar provides an introduction to the use of code coverage in today’s HDL design and verification flows.