Advanced UVM Debugging
On-demand Web Seminar
As designs continue to grow in complexity, the testbenches to verify those designs are growing right along with them. A recent study shows that, on average, verification engineers spend more time on debug than on any other task, including creating and running the tests. The use of UVM and SystemVerilog to create object-oriented testbenches has magnified the need for a good debugging solution to allow engineers to focus on verifying the design, not fixing problems in the testbench. This web seminar will highlight some new strategies for debugging UVM-based testbenches using Questa 10.2.
What You Will Learn
- How to debug common problems with the UVM configuration database
- How to see what types the factory has created for certain components
- How to visualize and analyze transactions as waveforms
- How to call UVM methods from the command-line to aid in information gathering
- How to create, manage and analyze UVM messages to aid in debug
About the Presenter
Tom Fitzpatrick is currently a Verification Technologist at Mentor Graphics Corp. where he brings over two decades of design and verification experience to bear on developing advanced verification methodologies, particularly using SystemVerilog, and educating users on how to adopt them. He has been actively involved in the standardization of SystemVerilog, starting with his days as a member of the Superlog language design team at Co-Design Automation through its standardization via Accellera and then the IEEE, where he has served as chair of the 1364 Verilog Working Group, as well as a Technical Champion on the SystemVerilog P1800 Working Group. At Mentor Graphics, Tom was one of the original designers of the Advanced Verification Methodology (AVM), and later the Open Verification Methodology (OVM), and is the editor of Verification Horizons, a quarterly newsletter with approximately 40,000 subscribers. He is a charter member and key contributor to the Accellera Verification IP Technical Subcomittee. He has published multiple articles and technical papers about SystemVerilog, verification methodologies, assertion-based verification, functional coverage, formal verification and other functional verification topics.
Who Should Attend
- Design Verification Engineers and Managers
What do I need to watch and hear this web seminar?
Mentor Graphics’ web seminars are delivered using Adobe Connect. You will be able to login to the seminar room 15 minutes prior to the start time on the day of the presentation. You can hear the audio using your computer’s speakers via VoIP (Voice over IP) and background music will play prior to the beginning of the presentation.
Detailed system requirements
- Windows XP, Windows Vista, Windows 7, Windows 8
- Microsoft Internet Explorer 7, 8, 9, 10; Mozilla Firefox; Google Chrome
- Adobe® Flash® Player 10.3 or later
- 1.4GHz Intel® Pentium® 4 or faster processor and 512MB of RAM
Mac OS X, 10.5, 10.6, 10.7.4, 10.8
- Mozilla Firefox; Apple Safari; Google Chrome
- Adobe Flash Player 10.3
- 1.83GHz Intel Core™ Duo or faster processor and 512MB of RAM
- Ubuntu 10.04, 11.04; Red Hat Enterprise Linux 6; OpenSuSE 11.3
- Mozilla Firefox
- Adobe Flash Player 10.3
- Apple supported devices: iPad, iPad2, iPad3; iPhone 4 and 4 S, iPod touch (3rd generation minimum recommended)
- Apple supported OS versions summary: iOS 4.3.x, 5.x, or 6.x (5.x or higher recommended)
- Android supported devices: Samsung Galaxy Tab 2 (10.1), Samsung Galaxy Tab (10.1), ASUS Transformer, Samsung Galaxy Tab (7”) , Motorola Xoom, Motorola Xoom 2, Nexus 7
- Android supported OS versions summary: 2.2 and higher
- Android AIR Runtime required: 3.2 or higher
- Bandwidth: 512Kbps for participants, meeting attendees, and end users of Adobe Connect applications. Connection: DSL/cable (wired connection recommended) for Adobe Connect presenters, administrators, trainers, and event and meeting hosts.
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