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Overview

• Are you getting anywhere near 100% functional coverage of your FPGA or ASIC netlist?
• Do you have mission critical blocks that require extensive functional validation?
• Are you spending multiple hours on FPGA implementation just to find functional issues?

Solution: Decrease your Time to FPGA Results with ASIC techniques like Equivalence checking. Using Equivalence checking can give you higher functional coverage, 100x faster than simulation. Equivalence checking will verify the tools in the flow, formally validate your process steps, revision control, and user modifications. Even real time FPGA prototyping tests will not cover 100% of the functionality, but equivalence checking can.

Why: Recent advancements in equivalence checking for FPGA's have brought a significant boost in operational usage efficiency. You can practice, learn and see how Equivalence Checking for FPGA's benefits you in the time it takes to do one large FPGA synthesis and implementation run.

This is a very small class, and we can spend time on your specific application. Related tool: FormalPro

Time: 11am - 2pm Lunch included

Agenda:

• How EC works
• Benefits of EC in a FPGA flow
• Lab 1: FPGA compile and verify using Precision FVI setup file with FormalPro
• Lab 2: Post Place&Route verification of Xilinx/Altera/Actel routed netlist
• Your application questions