Advanced Functional Verification Seminar
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Overview
This is the first session of a series of functional verification seminars . This seminar introduces methodology, technologies, and languages in today's verification solutions. SystemVerilog is the open-standard language used to define the solutions in this seminar. The subject also includes introductory concepts in base class libraries, assertion technologies, and advanced generation technologies which can be leveraged to solve real world challenges.Who Should Attend
- Verification & Design Engineers
- Verification & Design Managers
What You Will Learn
This seminar will focus on the latest methodologies in the functional verification of hardware logic designs. Todays challenges include the application and integration of many technologies and tools to form a methodology that is both thorough and efficient. Attendees will be introduced to concepts that can be implemented with open-standards, such as SystemVerilog. With the exponential growth in verification complexity, coverage driven management in verification is required to be successful in modern development projects. This concept will be discussed in the context of new techniques and tools available in the EDA industry today.
Location Details- Time: 11:00 AM - 1:00 PM
- Location: Hilton Atlanta, Northeast, 5993 Peachtree Industrial Blvd., Norcross, Georgia 30092