Assertion Libraries: Increased Environment Effectiveness and Thoroughness through Checkers and Monitors Seminar
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Overview
This seminar introduces the OVL and QVL assertion library. Topics include SVA constructs, property assertion and coverage, discussion of when and how to use SVA vs. an assertion library component, binding assertions into an environment and debugging with assertions.Who Should Attend
- Verification & Design Engineers
What You Will Learn
This seminar introduces the application of "assertions", using pre-packaged libraries such as the Open Verification Library (OVL) and the Questa Verification Library (QVL). Assertion libraries can be leveraged to efficiently integrate concise and accurate checking mechanism s in a verification environment. The QVL library extends OVL with numerous protocol and interface checkers above and beyond the base OVL library. The seminar will include information on how to apply assertions to Verilog and VHDL designs, and how to bind the checkers to designs within a verification environment.