Sign In
Forgot Password?
Sign In | | Create Account

Assertion-Based Verification to Improve Your FPGA Debug and Design Quality



The size and advanced features in today’s FPGAs have increased dramatically to a point where they can now compete with capabilities traditionally offered by ASICs alone. Accompanying all of these features and capabilities is a complexity in verification which traditional FPGA design flows are generally not prepared to address. Adopting assertion-based verification (ABV) can improve design quality through providing a “window” allowing active monitoring of functional correctness deep inside the design. Assertions catch errors that tests activate but fail to propagate to typical observation points; such as the primary outputs or interface signals. The assertions also turbo-charge time-to-debug productivity because they identify functional bugs much closer to the root cause; significantly shortening the causality traceback by hours or even days. ModelSim DE and Questa Core enable ABV through support of SystemVerilog Assertion (SVA) constructs and the Property Specification Language (PSL).

What You Will Learn

  • The value of Assertion-Based Verification in your FPGA design flow
  • Overview of the language and constructs for using assertions
  • Overview of the debug and GUI capabilities in ModelSim DE and Questa Core for using and debugging assertions
  • Demonstration of assertions in action and an example of a typical hard to find bug/problem that they are capable of easily identifying

About the Presenter

Presenter Image Walter Gude

Walter has over 25 years of experience in ASIC/FPGA design and holds a MS in Electrical Engineering from Washington University in St. Louis. He worked for 6 years doing ASIC design at Tellabs Operations. From there, he went to work for Mentor Consulting where he consulted on various ASIC projects including time spent in Munich Germany and Helsinki Finland. For the last decade, Walter has worked as an Application Engineer supporting Mentor's line of Functional Verification Projects.

Who Should Attend

  • FPGA Designer
  • FPGA Verification Engineer
  • FPGA Manager

Products Covered


What is an Assertion

Assertions Language Features

Assertion Examples

Assertion Libraries OVL

Assertion Binding

Assertion Debug with ATV


Online Chat