Automatic Formal Check Seminar

Seminar
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There are currently no dates scheduled for this event.

Overview

Automatic formal check uses formal verification to check the sequential behavior of a design and to look for common design issues. It leverages the power of formal verification with little effort from the users. Assertion rules are built into the tool. The checks are performed automatically and the results are presented graphically. Users do not need to write or debug any assertion property. It is ideal for project teams who are new to formal verification.

Lunch included at seminar.

What You Will Learn

  • Basic formal verification
  • The types of automatic checks
  • Basic tool features and usage

About the Presenter

Presenter Image Mark Eslinger

Mr. Eslinger has over 20 years of experience in chip design & verification, pre/post sales support, and technical marketing. As a technical marketing specialist in the Design Verification Technology Division of Mentor Graphics Mr Eslinger has a special focus on assertion-based methods and formal verification. In this role he works with customers worldwide to help them adopting advanced methodologies. Prior to Mentor Mr. Eslinger has held positions in the engineering and technical marketing organizations in the semiconductor, systems and EDA industry, including Lockheed, Synopsys, Abstract, Sente/Sequence, Averant, and AccelChip. Mr Eslinger holds a MSEE from Santa Clara University.

Who Should Attend

  • FPGA & ASIC Design and Verification Engineers and Managers

Products Covered

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