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Automating the Creation of Your UVM Register Model

Overview

The UVM Register Layer is a great way to abstract the interaction between your testbench and your DUT from the pin-level, or even protocol-specific transactions to a generic register-based view of communication. This abstraction provides many benefits, not the least of which is isolating your stimulus generation and coverage modeling from low-level changes in your design (i.e. separating the what from the how). Unfortunately, the benefits of using the register layer come at the cost of having to specify the register models in your testbench to reflect the registers in your hardware. With thousands or even tens of thousands of registers in a typical design, this can be a laborious and error-prone process when done from scratch. This webinar will introduce the Register Assistant feature of the Questa Verification Platform and show how it can be used to quickly generate correct-by-construction register models and tests from a register specification.

What You Will Learn

  • Brief review of the UVM Register Layer data model
  • Creating a spreadsheet-based Register Specification
  • Generating the register model code
  • Modifying your Register Specification
  • Adding Coverage and other advanced capabilities to your register model

About the Presenter

Presenter Image Tom Fitzpatrick

Verification Technologist

Tom Fitzpatrick is currently a Verification Technologist at Mentor Graphics Corp. where he brings over two decades of design and verification experience to bear on developing advanced verification methodologies, particularly using SystemVerilog, and educating users on how to adopt them. He has been actively involved in the standardization of SystemVerilog, starting with his days as a member of the Superlog language design team at Co-Design Automation through its standardization via Accellera and then the IEEE, where he has served as chair of the 1364 Verilog Working Group, as well as a Technical Champion on the SystemVerilog P1800 Working Group. At Mentor Graphics, Tom was one of the original designers of the Advanced Verification Methodology (AVM), and later the Open Verification Methodology (OVM), and is the editor of Verification Horizons, a quarterly newsletter with approximately 40,000 subscribers. He is a charter member and key contributor to the Accellera Verification IP Technical Subcomittee. He has published multiple articles and technical papers about SystemVerilog, verification methodologies, assertion-based verification, functional coverage, formal verification and other functional verification topics.

Who Should Attend

  • Verification Engineers and Managers

Technical Requirements

What do I need to watch and hear this web seminar?

Mentor Graphics’ web seminars are delivered using Adobe Connect. You will be able to login to the seminar room 15 minutes prior to the start time on the day of the presentation. You can hear the audio using your computer’s speakers via VoIP (Voice over IP) and background music will play prior to the beginning of the presentation.

Detailed system requirements

Microsoft® Windows

  • Windows XP, Windows Vista, Windows 7, Windows 8
  • Microsoft Internet Explorer 7, 8, 9, 10; Mozilla Firefox; Google Chrome
  • Adobe® Flash® Player 10.3 or later
  • 1.4GHz Intel® Pentium® 4 or faster processor and 512MB of RAM

Mac OS X, 10.5, 10.6, 10.7.4, 10.8

  • Mozilla Firefox; Apple Safari; Google Chrome
  • Adobe Flash Player 10.3
  • 1.83GHz Intel Core™ Duo or faster processor and 512MB of RAM

Linux

  • Ubuntu 10.04, 11.04; Red Hat Enterprise Linux 6; OpenSuSE 11.3
  • Mozilla Firefox
  • Adobe Flash Player 10.3

Mobile

  • Apple supported devices: iPad, iPad2, iPad3; iPhone 4 and 4 S, iPod touch (3rd generation minimum recommended)
  • Apple supported OS versions summary: iOS 4.3.x, 5.x, or 6.x (5.x or higher recommended)
  • Android supported devices: Samsung Galaxy Tab 2 (10.1), Samsung Galaxy Tab (10.1), ASUS Transformer, Samsung Galaxy Tab (7”) , Motorola Xoom, Motorola Xoom 2, Nexus 7
  • Android supported OS versions summary: 2.2 and higher
  • Android AIR Runtime required: 3.2 or higher

Additional requirements

  • Bandwidth: 512Kbps for participants, meeting attendees, and end users of Adobe Connect applications. Connection: DSL/cable (wired connection recommended) for Adobe Connect presenters, administrators, trainers, and event and meeting hosts.

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