Analyzing Bus Architectures for ARM-based SOC Designs

Online Event Registration

Click Here to Register and View Today!

Overview

The performance bottleneck of multiprocessor-based SoC designs is often limited by the bus architecture and topology that is chosen. Finding an efficient bus architecture early in the design can be not only difficult but critical to achieve the desired system performance while balancing to keep cost, power and area requirements to a minimum. This seminar presents a simulation-based approach for profiling and analysis to identify bottlenecks within a design's bus architecture; it also explains the impact that these bottlenecks have on the overall performance and throughput of the design. By using a simulation-based profiling and analysis approach, we explore the impact of different techniques, including software, HW/SW partitioning trade-offs, and bus topologies to improve the throughput and performance of multiprocessor-based SoC designs.

Who Should Attend

What You Will Learn