Clock-Domain Crossing Verification for FPGAs Seminar
There are currently no dates scheduled for this event.
Overview
Today FPGA designers are equally plagued by clock-domain crossing (CDC) problems as are ASIC designers. Simulation alone doesn't catch the CDC bugs, resulting in an extremely difficult and time-consuming debug process in the lab. This seminar teaches attendees about the types of problems associated with clock-domain crossings, the things you can do to avoid these issues, and how to apply an automated verification solution to ensure your FPGA is free of CDC issues. Questa CDC supports the leading FPGA vendors. Includes a demonstration.
Sign up today, seating is limited!
Time: 11:00 am - 1:00 pm
Complimentary lunch will be served.
What You Will Learn
- Which problems are associated with clock-domain crossings
- How to avoid these issues
- How to apply an automated verification solution to ensure your FPGA is free of CDC issues
About the Presenter
Kurt Takara
Mr. Takara has over 20 years of experience in engineering design and verification, technical marketing and engineering services. He is a Technical Marketing Engineer at Mentor Graphics Corporation and specializes in assertion-based verification methods and applications, including formal and clock-domain crossing (CDC) verification. Takara has held engineering, marketing, consulting services and project management roles in electronics and EDA companies such as Synopsys, Ikos Systems, Raytheon and Magnavox. He holds a BSEE from Purdue University and an MBA from Santa Clara University.
Who Should Attend
- Managers, designers, verification engineers of multi-clock designs