Mentor Graphics delivers the most comprehensive and unified advanced verification portfolio available: including Questa® for high performance simulation and debug, verification management and coverage closure, low-power verification with UPF, CDC, Formal Verification, accelerated functional coverage, processor-based hardware verification and Veloce® for high-performance system verification.
This portfolio combined with Mentor’s Vista™ ESL platform allows design and verification at higher levels of abstraction. This comprehensive solution supports UVM and OVM with the most comprehensive online Verification training available from Verification Academy.
Learn more about our design & verification solutions at DVCon by attending the following activities
Wednesday Conference Panels
Is Software the missing piece?
System-level verification has become an endemic problem. Verification budgets are stretched with increasing SoC verification complexity, and teams are looking for ways to improve the productivity of their verification efforts. Vendors are attempting to automate SoC verification through software-driven verification using a variety of approaches. Hear from Mark Olen and other panelists.
Did we create the Verification Gap?
The “Verification Gap” between what we need to do and what we’re actually able to do to verify large designs is growing each year. We must do our best to improve our verification methods and tools before our entire project schedule is taken up by verification tasks. Hear from Harry Foster and other panelists.
Exhibits & Product Demos
Monday | March 3rd | 5:00pm - 7:00pm
Tuesday | March 4th | 2:30pm - 6:00pm
Wednesday | March 5th | 2:30pm - 6:00pm
Mentor Graphics delivers the most comprehensive and unified advanced verification portfolio available: including Questa® for high performance simulation and debug, verification management and coverage closure, low-power verification with UPF, CDC, Formal Verification, accelerated functional coverage, processor-based hardware verification and Veloce® for high-performance system emulation. This comprehensive solution supports UVM and OVM.
We look forward to see you at DVCon 2014!
We have more than 15 papers and posters being presented during the conference discussing; Coverage, UVM, Verification IP, Debugging, Formal, Metrics Analysis and more!
Monday | March 3rd | 9:00am - Noon
Using UPF for Low Power Design and Verification
This tutorial presents the latest information on the Unified Power Format (UPF), beginning with a review of the concepts, terminology, commands, and options provided by UPF, it will cover the full spectrum of UPF capabilities and methodology, from basic flows through advanced applications, with particular focus on incremental adoption of UPF.
Thursday | March 6th | 8:30am - Noon
Block to System Verification: Smooth Sailing from Simulation to Emulation
With exploding design complexity, verification today requires effective use of a combination of tools and techniques together with methodology and a plan. This tutorial will focus on how multiple verification engines including simulation, formal, emulation and FPGA prototyping can be applied to objectives from block to system-level in order to achieve better verification results faster. Throughout the tutorial, real examples of customer use cases will be described.
Thursday | March 6th | 2:00pm - 5:30pm
Formal Verification in Practice: Technology, Methods and Applications
Attendees of this tutorial will learn how formal-based technologies are boosting verification efficiency in multiple domains including fully automatic, formal-based solutions, automated formal apps and property checking. The session will include a review of the technology behind these solutions, the industry best practices and user case studies.
Injecting Automation into Verification – Improved Throughput
Improving productivity has many forms, simulation performance, debug effectiveness, even writing test scenarios. We will highlight high value techniques for improving throughput.
Injecting Automation into Verification - Assertions
What we will show in this webinar is how we can leverage Assertions, including the pre-defined, pre-tested OVL libraries, to automate the verification process further. What we will also show is the way...
Injecting Automation into Verification – Code Coverage
This webinar provides an introduction to the use of code coverage in today’s HDL design and verification flows.