Effective Verification of Freescale Secure Communications Processors

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Overview

Freescale's next generation communications processors include an integrated security engine. As more commerce moves on-line, open, 'best-effort' IP infrastructure is no longer sufficient. An increasing percentage of network traffic is being protected by security protocols such as IPSec, SSL, SSH, and these security protocols make use of computationally intensive cryptographic algorithms. Without hardware acceleration, these cryptographic algorithms would consume too much system packet processing bandwidth, bringing network traffic to a crawl. Freescale's MPC8548E secure communication processor allows system designers to offer high performance, secure systems, at a fraction of the cost of discrete solutions.

Mentor Graphics Seamless® hardware/software co-verification is available today to help you accelerate your PowerQUICC processor-based systems to market. Seamless is proven to reduce risk in embedded system development by performing system integration months before a hardware prototype is available. Seamless co-verification is an ideal environment for analyzing system throughput and identifying performance bottlenecks.

Who Should Attend

  • Hardware Designers
  • Software Developers
  • Firmware Engineers
  • System Architects

What You Will Learn

  • The key technical benefits of the MPC8548E architecture
  • Verify your hardware using a fully functional PowerQUICC model with an integrated debugger
  • Validate software before the hardware prototype is available
  • Utilize optimizations to improve simulation throughput
  • Reduce time in the integration lab once hardware is delivered
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