Eliminating Clock-Domain Crossing Bugs with 0-In CDC

Overview

Most ASIC and FPGA designs on the drawing board today have multiple asynchronous clocks. With traditional simulation and static timing based methodologies coming up short in verifying the interaction between asynchronous clock domains, designers are looking for clock-domain crossing (CDC) verification solutions that address all CDC issues. This half-day workshop teaches you about the types of problems associated with clock-domain crossings, the things you can do to avoid these issues, and the application of an automated verification solution that ensures your design is free of CDC problems. Using the industry's benchmark CDC verification tool you will gain direct, hands-on experience finding and debugging hard-to-find CDC issues-experience you can apply immediately on your current design project.

Seating is VERY limited to maximize your learning experience, so submit your interest immediately to request your spot. This workshop includes lunch. (11:00 AM - 2:00 PM).

Who Should Attend