Embedded SoC Performance and Time to Market Webcast
There are currently no dates scheduled for this event
Overview
Take advantage of the highest performance, synthesizable, 32-bit cores in the embedded industry while minimizing design time and reducing product costs. With Seamless hardware/software co-verification from Mentor Graphics, you can fully verify and optimize your hardware and software interactions of your MIPS-based™ design. Performance profiling capabilities allow you to accurately measure the key design performance parameters, such as bus, memory and software performance, before committing to hardware.Tailored SoC design methodologies, an Open Core Protocol (OCP) interconnect structure, standard libraries and on-chip memories from industry-leading companies ensure that products based on 24K cores are brought to market with speed, ease and efficiency. The 24K family is the ideal solution for digital and interactive television, set-top boxes, DVD and other performance-driven applications.
Who Should Attend
- Hardware Designers
- Firmware Developers
- Verification Engineers
- System Integrators
- Engineering Managers
What You Will Learn
- Capitalize on the benefits of the embedded industry's highest-performance, synthesizable family of 32-bit cores
- Utilize SW development and debugging tools in a co-verification environment
- Ensure meeting performance goals and maximize the efficiency of your design
- Co-verify hardware and software with the cycle accurate models from Mentor Graphics and MIPS Technologies
- Speed simulations while creating a more flexible and comprehensive verification environment than logic simulation alone