Equivalence Checking for FPGA Designs Seminar
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Overview
When FPGA designs are large and complex, the deliverable design can no longer be verified completely with bench-test or gale-level simulation. FPGA projects can get trapped in the lab or risk shipping bugs without complete verification. Formal Equivalence Checking can transfer the coverage metric achieved in RTL simulation to the final netlist and verify the correct operation of synthesis and routing tools with fast static analysis. FPGA equivalence check is a challenge, and correct tool selection is important to meet the task.
Sign up today, seating is limited!
Time: 10am - 1:00pm US/Pacific
What You Will Learn
- When to use Equivalence Check in a FPGA flow
- How to control Synthesis for Formal Verification; How to interpret LEC results
- How to compute verification coverage
- Comparing FPGA build to an ASIC build
About the Presenter
Jim Henson
Jim is the manager of Engineering and Marketing for the FormalPro Equivalence Check product line. Jim was a hardware/ASIC designer for military electronics and hard disk drive companies from 1983-2004 and joined the Mentor Graphics Formal Verification group in 2004. Jim has seven patents for disk controller electronic developments. Education: BSEE, 1983, Oregon State University; MSEE 1988, Santa Clara University.
Who Should Attend
- Managers, Designers, Engineers