Fast and Accurate Formal Verification: Making Debug Easier Webcast
Online Event RegistrationClick Here to Register and View Today!OverviewThis webcast examines some of the major issues that affect the performance and effectiveness of formal verification in the real world. Formal verification provides huge benefits in reducing ASIC verification time, and reducing respins through comprehensive verification. However, it also provides challenges, which we will discuss in this presentation. Of particular interest is how to avoid numerous reports indicating differences in correct designs, and what to do once genuine errors are identified. The presentation will examine some particular features of Mentor’s advanced debug capabilities that allow a designer to trim weeks off the time required to correct errors in a design, and therefore get the ASIC to market earlier. Prerequisites: None Who Should Attend
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