Formal Verification Hands-on Workshop
Mentor Graphics Questa Formal Verification is being used by both design and verification engineers to improve design quality and accelerate verification. Questa Formal applications use assertion generation and formal verification to quickly and thoroughly verify specific design requirements or tool assumptions that would otherwise be tedious and time-consuming to address. Assertion-based verification enables verification of critical functionality such as control logic to ensure that failures cannot occur. Questa Formal allows early verification and is essential in improving quality of mission critical components and reducing simulation verification cycles. Post-silicon debug using formal verification makes it possible to quickly discover the root cause of an observed failure and confirm that a proposed fix is correct. This workshop will deliver an overview of Questa Formal Verification followed by a hands-on experience.
What You Will Learn
- The 4 primary applications of Questa Formal for improving your design verification and closure
- How Questa Formal is complimentary to Questa Simulation and how the two together can accelerate your results
- Easy methods to incorporate Questa Formal into your design and verification flow
- How to run Questa Formal with a step by step hands-on exercise using a simple example
Who Should Attend
- Design and Verification Engineers and Managers
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