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FPGA Verification Forum 2012

Overview

Today’s FPGAs are where ASICs were 10 years ago. You can no longer meet schedules and deliver designs on time with a simple milestone of being “in the lab”. This event will take you on a journey to employ new techniques to get your projects out faster and with fewer problems. It is a like a train journey with various stops. You can choose to get off at the first stop or go all the way to the last stop. Either way, you will benefit and reach your ultimate goal.

What You Will Learn

  • Why you need a Verification Process
  • Three Steps to injecting Automation
  • Reduce debug Time by 50%
  • Understand where you are in the Verification Process
  • Build an effective Testbench Infrastructure
  • ModelSim GUI Essentials - with Demonstrations
  • Performance Tuning: Tips & Tricks

Agenda

Eindhoven, Stuttgart, Berlin

  • 09:00 – 09:30
    Registration
  • 09:30 – 09:40
    Welcome and Introduction
  • 09:40 – 09:50
    Why do you need a Verification Process, Harry Foster
  • 09:50 – 10:00
    Three Steps to injecting Automation, Harry Foster
  • 10:00 – 10:45
    Reduce debug Time by 50%, Harry Foster
  • 10:45 – 11:15
    Coffee Break
  • 11:15 – 12:00
    Understand where you are in the Verification Process, Harry Foster
  • 12:00 – 12:45
    Build an effective Testbench Infrastructure, Joe Rodriguez
  • 12:45 – 13:00
    Summary, Harry Foster
  • 13:00 – 14:00
    Lunch Break
  • 14:00 - 14:45
    ModelSim GUI Essentials - with Demonstrations, Neil Rattray
  • 14:45 – 15:30
    Performance Tuning: Tips & Tricks, Joe Rodriguez
  • 15:30 – 15:45
    Wrap-up and Closing

Warsaw

  • 09:00 – 09:30
    Registration
  • 09:30 – 09:40
    Welcome and Introduction
  • 09:40 – 09:50
    Why do you need a Verification Process, Joe Rodriguez
  • 09:50 – 10:00
    Three Steps to injecting Automation, Joe Rodriguez
  • 10:00 – 10:45
    Reduce debug Time by 50%, Joe Rodriguez
  • 10:45 – 11:15
    Coffee Break
  • 11:15 – 12:00
    Understand where you are in the Verification Process, Joe Rodriguez
  • 12:00 – 12:45
    Build an effective Testbench Infrastructure, Joe Rodriguez
  • 12:45 – 13:00
    Summary, Joe Rodriguez
  • 13:00 – 14:00
    Lunch Break
  • 14:00 - 14:45
    ModelSim GUI Essentials - with Demonstrations, Neil Rattray
  • 14:45 – 15:30
    Performance Tuning: Tips & Tricks, Joe Rodriguez
  • 15:30 – 15:45
    Wrap-up and Closing

 

Thatcham

  • 09:00 – 09:20
    Welcome and Introduction
  • 09:20 – 09:30
    Why do you need a Verification Process, Joe Rodriguez
  • 09:30 – 09:40
    Three Steps to injecting Automation, Joe Rodriguez
  • 09:40 – 10:25
    Reduce debug Time by 50%, Joe Rodriguez
  • 10:25 – 11:00
    Understand where you are in the Verification Process, Joe Rodriguez
  • 11:00 – 11:30
    Coffee Break
  • 11:30 – 12:15
    Build an effective Testbench Infrastructure, Joe Rodriguez
  • 12:15 – 12:30
    Summary, Joe Rodriguez
  • 12:30 – 12:45
    Wrap-up and Closing
  • 12:45 – 1:30
    Lunch

About the Presenters

Presenter Image Harry Foster

Harry Foster is Chief Scientist for the Mentor Graphics Design Verification Technology Division. He holds multiple patents in verification and has co-authored seven books on verification. Harry was the 2006 recipient of the Accellera Technical Excellence Award for his contributions in developing industry standards, and was the original creator of the Accellera Open Verification Library (OVL) standard.

Presenter Image Joe Rodriguez

Joe Rodriguez is a FPGA Market Development for Design Verification Technology (DVT) division at Mentor Graphics. Prior to this role Joe spent 2 years as Technical Marketing Manager for the Emulation Division (MED) at Mentor Graphics. Joe was also the Technical Marketing Manager in DVT at Mentor Graphics for 12 years. A result of this Joe has been involved in the definition and creation of many aspects of the Mentor Graphics verification solutions. Solutions like power aware simulation, debug and performance flows, including US patents for simulation event reduction.

Prior to Mentor Graphics, Joe spent 5 years as a field application engineer for Quickturn Design Systems successfully deploying many large FGPA based emulation projects. Joe also spent 6 years at Logic Automation as a Modeling Engineer and Support Manager. Joe has 7 years experience as a diagnostic engineer at Floating Point System and holds a Bachelor of Science in electrical engineering.

Who Should Attend

  • FPGA Designer
  • Verification Engineer
  • Project Manager
  • Development Manager

Products Covered

Related Resources

 
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