The Hitchhiker's Guide to Verification Seminar

There are currently no dates scheduled for this event.

Overview

Having a very bad day? Your last chip required a respin, you just realized that there's a whole class of bugs that your testbench just isn't set up to catch, and to top things off, you don't have enough verification engineers to write all the tests you're going to need.

DON'T PANIC!

Your only chance for survival: hitch a ride with a friendly team of verification experts. With The Hitchhiker's Guide to Verification seminar, you'll set out on a journey in which you'll find the secret to Life, the Universe and Everything (or at least the secret to Testbench Automation, Reuse, and Functional Coverage).

In this one-day seminar, you'll discover how the right verification methodology is more useful than a Babel Fish, and can ultimately be the key to understanding and productivity between your design, verification, software and systems teams. More efficient than a fleet of Vogons building a hyperspace bypass, The Hitchhiker's Guide to Verification will teach you everything you need to know to apply the latest verification techniques to solve your most pressing problems.

Set up mostly in two parallel tracks, the day will begin with an introduction to Mentor Graphics' Advanced Verification Methodology (AVM), which greatly facilitates the development of transaction-level testbenches that can be used to verify designs at multiple levels of abstraction. After that, we break into two more-focused tracks.

Agenda

8:30 - 9:00	Registration
9:00 - 10:30	Introduction & Verification Methodology (General session)
10:30 - 10:45	Break
	Track A (see details below)	Track B (see details below)
10:45 - 12:15	Testbench Automation & Coverage	SystemVerilog Assertions
12:15 - 1:00	Lunch
1:00 - 2:30	Advanced Stimulus Generation	Formal analysis and clock-domain verification
2:30 - 3:00	Closing/Q&A panel (General Session)

Track A
Track A will go into much more detail on how the AVM can be deployed to facilitate testbench reuse and get you up and running and applying such concepts as functional coverage quickly. After lunch, the track will discuss advanced techniques for constrained-random stimulus generation and how to apply them in the context of the AVM.

Track B
Track B will focus more on the use of assertions and formal verification. After an in-depth discussion of SystemVerilog assertions and how to apply them in both simulation and formal verification, the afternoon session will show you how to solve your clock-domain crossing issues and how to apply formal verification to find bugs and increase your coverage.

To close the session, we will hold a Q&A panel session with all of the instructors to provide you an opportunity to get answers to any questions you may have, or advice on how to apply the lessons learned to your particular environment.