Injecting Automation into FPGA Verification Seminar
The definition of what FPGA really means has changed dramatically over the last two decades. Whether blazing the trail or being on the trailing edge of Moore's Law, this is an exciting time to be an FPGA Designer. New opportunities bring new challenges for the FPGA market. As devices grow and become more complex resembling complete systems, the task of verifying such a system becomes daunting.
Mentor Graphics can help. By providing the latest technology for improving debugging, providing coverage, and improving verification throughput, we have the needed tools and expertise to get your products out the door faster and with higher quality. This 3-part seminar will help you get started with using code coverage for providing coverage, assertions for debug and techniques for improving verification throughput for improving the predictability of your development process.
- 8:30 - 9:00: Registration/Continental Breakfast
- 9:00 - 9:50: Keynote: The Verification Revolution: FPGA Trends and How to Keep Up - presented by Tom Fitzpatrick
- 9:50 - 10:40: Providing Coverage
- 10:40 - 10:50 Break
- 10:50 - 11:40: Improved Debug with Assertions
- 11:40 - 12:15 Lunch
- 12:15: 1:00: Improving Throughput
- 1:00 - 2:00: GUI Essentials
10:50 - 11:40: Providing Coverage
The first FPGA Verification session "Providing Coverage" describes code and functional coverage, and how each of these verification techniques can be applied to your verification process. Step by step adoption flows are presented. Answer questions about how coverage can improve FPGA lab productivity. What is the benefit of adding functional coverage?. What is the impact of code coverage? How to deploy new processes and manage FPGA project demands. Why does coverage matter and how to leverage FPGA verification process improvements.
12:15 - 1:00: Improving Throughput
The third FPGA Verification session "Improved Throughput" describes how you can leverage common techniques for accelerating your verification activities. A step by step process begins with a focus on how to build up transactions based on the functionality of your FPGA design's interface(s) to improve your test scenario generation and debug effectiveness. We will also describe how to maximize the performance of simulation so you can begin to think about HW/SW integration before going into the lab. We will also talk about improving the time it takes to verify external interfaces like PCIE and how to easily identify potential clock domain crossing bugs in your FPGA design so you can maximize your lab testing clock rates and design bring up.
1:00 - 2:00: GUI Essentials
There have been many improvements in the Graphical User Interface to aid the identification of issues, and debugging their root cause. The productivity improvements are very broad, from managing messages, source code browsing, Finite State Machine debug, waveform management. This session will give you a working knowledge of the most popular improvements.
About the Presenters
Tom Fitzpatrick is currently a Verification Technologist at Mentor Graphics Corp. where he brings over two decades of design and verification experience to bear on developing advanced verification methodologies, particularly using SystemVerilog, and educating users on how to adopt them. He has been actively involved in the standardization of SystemVerilog, starting with his days as a member of the Superlog language design team at Co-Design Automation through its standardization via Accellera and then the IEEE, where he has served as chair of the 1364 Verilog Working Group, as well as a Technical Champion on the SystemVerilog P1800 Working Group. At Mentor Graphics, Tom was one of the original designers of the Advanced Verification Methodology (AVM), and later the Open Verification Methodology (OVM), and is the editor of Verification Horizons, a quarterly newsletter with approximately 40,000 subscribers. He is a charter member and key contributor to the Accellera Verification IP Technical Subcomittee. He has published multiple articles and technical papers about SystemVerilog, verification methodologies, assertion-based verification, functional coverage, formal verification and other functional verification topics.
Joe Rodriguez is a FPGA Market Development for Design Verification Technology (DVT) division at Mentor Graphics. Prior to this role Joe spent 2 years as Technical Marketing Manager for the Emulation Division (MED) at Mentor Graphics. Joe was also the Technical Marketing Manager in DVT at Mentor Graphics for 12 years. A result of this Joe has been involved in the definition and creation of many aspects of the Mentor Graphics verification solutions. Solutions like power aware simulation, debug and performance flows, including US patents for simulation event reduction.
Prior to Mentor Graphics, Joe spent 5 years as a field application engineer for Quickturn Design Systems successfully deploying many large FGPA based emulation projects. Joe also spent 6 years at Logic Automation as a Modeling Engineer and Support Manager. Joe has 7 years experience as a diagnostic engineer at Floating Point System and holds a Bachelor of Science in electrical engineering.
Who Should Attend
- Verification Engineers and Managers
Injecting Automation into Verification – Improved Throughput
Improving productivity has many forms, simulation performance, debug effectiveness, even writing test scenarios. We will highlight high value techniques for improving throughput.
Injecting Automation into Verification - Assertions
What we will show in this webinar is how we can leverage Assertions, including the pre-defined, pre-tested OVL libraries, to automate the verification process further. What we will also show is the way...
Injecting Automation into Verification – Code Coverage
This webinar provides an introduction to the use of code coverage in today’s HDL design and verification flows.