Innovation in Verification Seminar - Abstracts

Make Functional Verification your Competitive Differentiator

Companies that master the functional verification challenges for today's chips have a competitive advantage in that they can get products to market faster. In this keynote we identify the core pieces of technology and methodology that not only maximize design quality, but also ensure maximum verification productivity. We will further show how Mentors scalable verification platform is uniquely positioned to deliver this next generation of verification productivity.

CDC Verification

Most ASIC and FPGA designs on the drawing board today have multiple asynchronous clocks. With traditional simulation and static timing based methodologies coming up short in verifying the interaction between asynchronous clock domains, designers are looking for clock-domain crossing (CDC) verification solutions that address all CDC issues. This session teaches you about the types of problems associated with clock-domain crossings, the things you can do to avoid these issues, and the application of an automated verification solution that ensures your design is free of CDC problems.

Verification Management

Verification management is one of the most important factors in today’s verification of silicon chips and SoC designs. Every development team manages their verification process in some way, but how easy it is to answer certain questions reveals the effectiveness and completeness of each approach in delivering on schedule. Where are we in the verification process? Are we ready to sign-off? If a change is made to a design block, which tests need to be re-run to get the best coverage? What affect on the verification process does a last minute change to my functional specification have? The fact that all of these questions are not easily answered by the vast majority of verification plans demonstrates the need for the automated storage and analysis of verification data within the verification process.

Open Verification Methodology (OVM)

This session covers the use and benefits of the Open Verification Methodology (OVM). The OVM brings together verification knowledge, experience and expertise to provide an approach to building verification IP and testbenches powerful enough to meet the most demanding requirements, yet easy to adopt. This session illustrates all aspects of the OVM, including the following: planning for verification, testbench architecture, transaction-level modeling in verification, sequential stimulus and coverage, and block-to-system-level reuse.

Processor Based Verification

Using a full-functional processor model to drive bus-cycles into a block or chip level simulation is a powerful method to verify SoC designs. Since the end product is processor driven, this “real world” approach to verification is superior to bus-functional models. This session will present the full range of processor driven methods from sign-off simulation using an RTL pin-level model to OVM transaction-level processor models. Included is a live demonstration of Questa Codelink, a tightly integrated source-level debugger for processor-driven tests.

TLM for SoC Design and Verification

To meet the ever increasing demand for electronic product performance, functionality, and cost designers of complex ICs use all available technological and computational power delivered by Moore's law and modern VLSI technology. These System-On-Chip (SoC) designs are built through the integration of large HW and SW blocks leveraging IP reuse and abstraction to manage complexity. This session presents an overview of Mentor Graphics evolutionary path from existing RTL based design and verification methods to an RTL/TLM co-development SoC platform with enabling technologies such as mixed-abstraction Multi-View Components and automated Power/Timing TLM model generation. We will further demonstrate the practical use of the Multi-View verification Components (MVCs) in an integrated RTL/TLM, OVM-based AMBA verification environment.

Low Power Verification

The advent of power aware design with various techniques for managing power consumption such as multi-voltage, power gating and dynamic voltage and frequency scaling increases the opportunities for functional problems and the challenge of verifying designs. Historically, verification of the functionality of power islands within the context of a power management scheme has been performed only at the gate level, if at all. However, waiting to perform verification and the corresponding resolution of bugs at the gate-level is too costly in terms of resources and design cycles. This session describes the basic elements of low power design and discusses how an industry standard -- Unified Power Format (UPF) -- along with innovative technology enable power-aware verification from RTL design through implementation.

Intelligent Testbench Automation

When asked about the state of functional verification, Gary Smith, founder and chief analyst for market research company Gary Smith EDA, commented, “Throwing engineers at the problem is not an acceptable answer. The target is to bring verification costs down to 35% of the total hardware design cost, and we can only do that through automation. The intelligent testbench is the missing ingredient in today’s verification flow.” In this session, you will learn about Mentor Graphics’ award-winning intelligent testbench automation product line called “inFact”. inFact employs advanced algorithms to improve testbench productivity and effectiveness by 10x to 100x. You’ll see inFact automatically generating testbench sequences for Questa Multi-View Verification Components (MVC’s) for simulation with Questa, all in the Open Verification Methodology (OVM). Then, inFact will send its functional coverage results into the Questa Unified Coverage Database (UCDB), for comprehensive coverage analysis and management reporting. Finally, as inFact achieves higher functional coverage in less time with fewer resources, you’ll see why inFact was awarded the Editor’s Choice Award for 2008 by Portable Design Magazine.

Formal Verification

As designs become more complex, achieving a high level of confidence in the correctness of the design becomes more challenging. As a result, many companies are looking to complement their simulation-based verification flows with formal verification. By targeting hard-to-verify verification hot spots like data integrity logic, complex state machines, interface controllers, etc. with formal verification, we show a practical and effective approach to adopting formal verification that will help find more bugs faster and raise the confidence in the correctness of your most critical blocks. Moreover, we show how, in conjunction with simulation, formal technologies help you reach your coverage goals more quickly and pinpoint post-silicon bugs more effectively.