Mentor Forum for Verification
There are currently no dates scheduled for this event.
As SoC and ASIC designs continue growing in both size and complexity and FPGA devices now becoming SoCs themselves, design and verification teams are constantly searching for ways to increase their verification productivity and design quality to keep up with this growing challenge. There have been several methodologies introduced in the past that are aimed at addressing these challenges. Accellera’s Universal Verification Methodology (UVM), with its library created in SystemVerilog, is the first methodology that incorporates lessons learned from those previous methodologies and is supported and endorsed by all three major EDA vendors in addition to a growing Eco-System of providers.
Engineers and managers want to understand how UVM will benefit them, what effort will it take to adopt, what is available to help, how they fit it into their current environment and do they have the right people to maximize its benefits.
Attend this seminar for a comprehensive introduction to UVM. Learn of how it can be used to significantly increase verification throughput and how tools available around it ease adoption and improve productivity.
What You Will Learn
This seminar will deliver a comprehensive overview of how UVM can be used for maximum verification throughput and the tools available around it to both ease adoption and improve productivity. During this seminar you will learn:
- Keys and techniques for effective Verification Planning and Management for UVM
- A staged approach for UVM adoption using UVM Express
- Tools and techniques to track Design Requirements through verification
- Tools and techniques to manage verification regression runs, track verification and simulation with a testplan, automatically analyze results, instantly understand status of projects, and analyze trends during verification
- Best practices and tools to create your UVM testbench and capabilities of UVM Verification IP
- Best practices and tools to effectively debug your UVM testbench alongside your design
- How to automate, track and accelerate coverage closure
- Complementing UVM with easy to use static tools for more comprehensive verification
About the Presenter
Harry Foster is Chief Scientist for the Mentor Graphics Design Verification Technology Division. He holds multiple patents in verification and has co-authored seven books on verification. Harry was the 2006 recipient of the Accellera Technical Excellence Award for his contributions in developing industry standards, and was the original creator of the Accellera Open Verification Library (OVL) standard.
Who Should Attend
- Design and Verification engineers looking to improve their verification by adopting UVM and existing UVM users looking to increase their UVM productivity further by incorporating UVM aware tools and techniques.
- Questa Codelink
- Questa® inFact
- Questa® Advanced Simulator
- Questa Power Aware Simulator
- Questa Verification Management
- Questa Verification IP
09:30 Registration and morning coffee
10:00 Keynote -, Increasing Productivity Within The Transforming World Of Functional Verification, Harry Foster, Mentor Graphics' Chief Scientist for verification
10:45 Effective Planning with UVM
13:30 Building, running, understanding your UVM Environment
15:00 Achieving Coverage Closure Faster with the UVM Methodology
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