ModelSim & Questa Seminar and Social

Seminar

There are currently no dates scheduled for this event.

Overview

Trilogic and Mentor Graphics invite you to come and learn about the new ModelSim DE! Modelsim DE Combines a Modelsim PE simulation engine with some of the high end debug features of the Modelim SE, along with System Verilog and PSL Assertions, all in an affordable package.

ModelSim DE at a glance:

  • Modelsim PE simulation engine
  • System Verilog and PSL Assertions
  • Linux / Windows Support
  • Code Coverage
  • Xilinx Secure IP Support in an affordable ModelSim Package
  • Dataflow Window
  • Waveform Compare

With this new Modelsim Bundle you can speed debug effectiveness by using System Verilog Assertions. Assertions monitor a condition in your simulation and report if an error is found. System Verilog assertion IP is available for free from Accellera.org for standard functions that can simply be instantiated in your test bench to monitor for errors. Assertions can easily be created to test for corner cases or exception handling.

 

This is both a seminar on ModelSim DE and a user networking social to meet and greet with the Trilogic/Mentor resources and other users.  The seminar will be held from 3:30 pm - 4:30 pm with the social following from 4:30 - 7:00 pm.  Food and beverages will be provided for the social following the seminar.

Presenter Image Walter Gude

Walter has 19 years experience in ASIC/FPGA design and holds a MS in Electrical Engineering from Washington University in St. Louis. He worked for 6 years doing ASIC design at Tellabs Operations. From there, he went to work for Mentor Consulting where he consulted on various projects including time spent in Munich Germany and Helsinki Finland. For the last 5 years Walter has worked as an Application Engineer supporting Mentor's line of Functional Verification Projects.

Who Should Attend

  • FPGA Design Engineers
  • Verification Engineers
  • Design Managers

What You Will Learn

  • How Assertion Based Verification improve verification effectiveness
  • How to Manage windows to get the most out of debug
  • How to compare simulation results to expose issues between revisions of a design
  • How to trace design issues to their sources using Enhanced Debug features
  • How to use advanced Code Coverage features including expression and conditional coverages
  • How to get support and find answers to questions

Products Covered