Design and Verification of Multi-processor SoCs

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Overview

Traditional SoCs use a processor for the control plane and IP logic blocks for most data-path functions. With the advent of small, fast configurable cores, processors and firmware are replacing some of the dedicated logic for audio and video data transform functions. Firmware in the data path demands new verification methods which support the co-simulation of logic and firmware in order to fully prove correct functionality. 

Tensilica's answer comes in the form of configurable processor flexibility. Configurable and pre-configured processor cores can perform on-chip processing while providing software programmability and RTL processing speeds. They also provide a nearly infinite number of software-compatible processors that span a wide performance and area range. 

Mentor Graphics Seamless product has been named the premier co-verification tool for Tensilica’s new Diamond Standard series of processor cores. Seamless provides designers with a virtual platform to debug hardware/software integration issues while increasing simulation throughput, thereby allowing designers to quickly validate that the system hardware and software are functionally correct before prototypes are manufactured. 

This online seminar walks you through the basics of these two product lines, explaining how they work in conjunction with one another to provide a complete solution to SoC design complexity.

Who Should Attend

What You Will Learn