Scalable Verification Online Events
FEATURED ONLINE SEMINARNext Generation Advanced Verification - view all 5 sessions These archived online seminars focus on the methodology, tools and infrastructure you'll need to handle those large verification projects. As designs become more complex, you may have the need for additional debug and speed capabilities in your simulation environment. In this seminar we will introduce the full ModelSim product line. We will show how ModelSim SE optimizations can dramatically increase the amount of simulation cycles a designer can simulate. Finally we will show how do decrease your time to debug with ModelSim Productivity Features like Dataflow and Code Coverage. If you are seeking increased functionality or just need a lot more performance to get your designs done, then this online seminar is for you. Time: 10:30 AM - 11:30 AM PST ModelSim Designer delivers a complete FPGA design and verification environment. Our focus is on improving your productivity which means the complete process of creation, management, simulation, and implementation is controlled from a single user interface, facilitating the design and verification flow and providing significant productivity gains. Single environment means a shorter learning curve so you can realize your vision faster.
To support synthesis and place-and-route, ModelSim Designer automatically manages your project files, easing the downstream transition to the synthesis and place-and-route tools of your choice. Connection of these additional tools is easy, giving FPGA designers control of simulation, design creation, synthesis, and place-and route from a single cockpit. ModelSim Designer is also very extensible with lots of options available like code coverage, SWIFT interface, and a profiler to identify your performance bottlenecks. This 30 minute multimedia presentation provides an overview of ModelSim Designer and demonstrates how to Mange the entire FGPA Design process and import and analyze Existing HDL code. For those leading-edge companies who have taken the plunge, assertion-based verification has fulfilled the promise of higher quality verification with fewer resources, better predictability, and reduced risk. So what's holding you back? This on-demand web seminar introduces design/verification engineers and management to the benefits and realities of assertion-based verification. Topics covered include:
During this seminar, you will be introduced to issues and powerful solutions to aid you in your move to ABV. These solutions include PSL, SVA, OVL, 0-In CheckerWare, 0-In monitors, 0-In CDC, and 0-In Formal Verification.
The Advanced Verification with Questa online seminar will provide an understanding of relevant advanced verification topics utilizing SystemVerilog that will dramatically improve verifying today's complex SoC designs. You will learn the concepts and techniques behind an advanced verification methodology that can immediately be applied to your current projects. These concepts include but are not limited to:
The first two segments of the seminar reviews the above concepts. The second portion of the seminar continues with a discussion of these topics to show what they can (and can't) contribute to a verification methodology, and what value the Questa verification platform provides for such a methodology. The seminar closes with showing how to architect and assemble a testbench to deploy these techniques. The performance bottleneck of multiprocessor-based SoC designs is often limited by the bus architecture and topology that is chosen. Finding an efficient bus architecture early in the design can be not only difficult but critical to achieve the desired system performance while balancing to keep cost, power and area requirements to a minimum. This seminar presents a simulation-based approach for profiling and analysis to identify bottlenecks within a design's bus architecture; it also explains the impact that these bottlenecks have on the overall performance and throughput of the design. By using a simulation-based profiling and analysis approach, we explore the impact of different techniques, including software, HW/SW partitioning trade-offs, and bus topologies to improve the throughput and performance of multiprocessor-based SoC designs. As a follow-on to Harry Foster's seminar "Integrating Functional Formal Verification into a Traditional Flow," in this seminar Harry dives down into the application of this methodology. Moving beyond theoretical discussions, this seminar will take you to the next level of understanding in the formal verification planning process. After introducing a systematic set of steps for effective formal verification planning, the discussion quickly moves beyond mere concepts by applying the process to a real detailed example of generating a comprehensive formal friendly property set. The conclusion of this seminar introduces four strategies you might choose from to verify your property set, depending on your goals and available resources. Presenter Bio: Harry Foster is a principle engineer for the Mentor Graphics Design, Verification, and Test division. Prior to joining Mentor, Harry was Jasper Design Automation's chief methodologist and Verplex Systems' chief architect. He currently serves as chair of the Accellera Formal Verification Technical Committee and chair of the IEEE 1850 Property Specification Language (PSL) working group. Harry is co-author of multiple books on verification and holds multiple patents in verification. He is the original creator of the Accellera Open Verification Library (OVL) assertion monitor standard and was the 2006 recipient of the Accellera Technical Excellence Award. Traditional SoCs use a processor for the control plane and IP logic blocks for most data-path functions. With the advent of small, fast configurable cores, processors and firmware are replacing some of the dedicated logic for audio and video data transform functions. Firmware in the data path demands new verification methods which support the co-simulation of logic and firmware in order to fully prove correct functionality. Tensilica's answer comes in the form of configurable processor flexibility. Configurable and pre-configured processor cores can perform on-chip processing while providing software programmability and RTL processing speeds. They also provide a nearly infinite number of software-compatible processors that span a wide performance and area range. Mentor Graphics Seamless product has been named the premier co-verification tool for Tensilicaâs new Diamond Standard series of processor cores. Seamless provides designers with a virtual platform to debug hardware/software integration issues while increasing simulation throughput, thereby allowing designers to quickly validate that the system hardware and software are functionally correct before prototypes are manufactured. This online seminar walks you through the basics of these two product lines, explaining how they work in conjunction with one another to provide a complete solution to SoC design complexity. Freescale's next generation communications processors include an integrated security engine. As more commerce moves on-line, open, 'best-effort' IP infrastructure is no longer sufficient. An increasing percentage of network traffic is being protected by security protocols such as IPSec, SSL, SSH, and these security protocols make use of computationally intensive cryptographic algorithms. Without hardware acceleration, these cryptographic algorithms would consume too much system packet processing bandwidth, bringing network traffic to a crawl. Freescale's MPC8548E secure communication processor allows system designers to offer high performance, secure systems, at a fraction of the cost of discrete solutions. Mentor Graphics Seamless® hardware/software co-verification is available today to help you accelerate your PowerQUICC processor-based systems to market. Seamless is proven to reduce risk in embedded system development by performing system integration months before a hardware prototype is available. Seamless co-verification is an ideal environment for analyzing system throughput and identifying performance bottlenecks. Clocking issues are the second leading cause of silicon respins. In today's multi-clock designs, errors relating to the management of clock-domain crossing (CDC) signals are difficult to find with traditional verification -- resulting in functional errors in silicon. This seminar will examine why CDC signals cause problems for verification, and how they can be identified, managed and verified using automated RTL analysis combining formal and simulation techniques. This webcast examines some of the major issues that affect the performance and effectiveness of formal verification in the real world. Formal verification provides huge benefits in reducing ASIC verification time, and reducing respins through comprehensive verification. However, it also provides challenges, which we will discuss in this presentation. Of particular interest is how to avoid numerous reports indicating differences in correct designs, and what to do once genuine errors are identified. The presentation will examine some particular features of Mentorâs advanced debug capabilities that allow a designer to trim weeks off the time required to correct errors in a design, and therefore get the ASIC to market earlier. Prerequisites: None This presentation provides an overview of the ARM Cortex A8 processor--a high-performance/low-power processor used in wireless, consumer, enterprise, and automotive applications--and discusses the benefits of using a virtual prototype to uncover potential errors in code prior to tape-out of designs using this processor. Presented jointly by ARM and Mentor Graphics engineers, you will learn how to address challenges facing design engineers dealing with power, performance, and area goals and how to uncover coding errors that would force costly re-spins. This presentation provides an overview of the ARM1176 processor--a high-performance/low-power processor used in wireless, consumer, enterprise, and automotive applications--and discusses the benefits of using a virtual prototype to uncover potential errors in code prior to tape-out of designs using this processor. Presented jointly by ARM and Mentor Graphics engineers, you will learn how to address challenges facing design engineers dealing with power, performance, and area goals and how to uncover coding errors that would force costly re-spins. Verification Expert, Harry Foster will present this seminar starting with a review of the inherent limitations of traditional verification flows-and how these limitations have contributed to the increasing number of functional failures in many of today's SoC designs. Building on this understanding, the seminar reviews how contemporary verification flows (such as assertion-based verification, constrained-random verification, coverage-driven verification, and functional formal verification) address many of the inherent limitations of traditional flows. Next, this seminar discusses guidelines for integrating functional formal verification into a traditional verification flow. Topics covered include:
This 45 minute multimedia presentation will walk the audience through various strategies for adopting an Advanced Verification. We will examine the different components including:
We will show how these techniques can be applied both incrementally to existing verification environments and in a proactive manner to build an infrastructure capable of taking full advantage of these powerful concepts. We will discuss various aspects of the verification problem, and show how the Questa verification platform provides the tool infrastructure required to support the methodology. This presentation will walk the audience through various strategies for adopting an Advanced Verification. We will examine the different components including:
...and show how these techniques can be applied both incrementally to existing verification environments and in a proactive manner to build an infrastructure capable of taking full advantage of these powerful concepts. We will discuss various aspects of the verification problem, and show how the Questa verification platform provides the tool infrastructure required to support the methodology. Presented by Walter Gude - Senior Application EngineerThis 60 minute multimedia presentation will go into the specific features that ModelSim PE and SE provide above what is available in the silicon vendor version of ModelSim commonly provided by Altera, Lattice and Xilinx. If you are seeking increased functionality or just need a lot more performance to get your designs done, then this online seminar is for you. These archived online seminars focus on the methodology, tools and infrastructure you'll need to handle those large verification projects. The successful completion of any System-on-Chip project is dependent on many complex, interrelated factors. Validation that the design is both functionally correct and meets system performance goals is a process of iterative refinement. To achieve the required results, you need a set of powerful design, analysis, and verification tools linked to a productive, easy to use flow. By identifying design bottlenecks and performance concerns - and automating their elimination - a new, tightly integrated SoC Design and Verification solution from Mentor Graphics addresses these fundamental challenges. An assemblage of specialized tools, this solution enables you to improve design productivity, design quality, project delivery schedules, and return on investment. This webinar presents a case study in which a customer applies this Mentor Graphics solution at each design phase; thus presenting the mechanics and the results of its application. As SoC design complexity and configurability increases, the need for combining IP efficiently from various sources is a requirement. The development and enablement of standards in platform-based design and IP reuse helps to reduce costs while improving product ease-of-use and integration flexibility. Mentor Graphics Platform Express enables designers to rapidly create and verify platform-based SoC designs by automating complex, tedious, error-prone design creation, and IP integration and verification steps. The ARM PrimeXsys Platform ease-of-use is enhanced by the robustness of the Platform Express system design methodology and the multi-vendor SPIRIT standard tool and IP support. Platform-based design based on these robust methodologies, IP-architecture and design-standards shaves months off aggressive product development cycles and allows designers to focus on product differentiating tasks. Having a bad day? Your last chip required a respin, you just realized that there's a whole class of bugs that your testbench isn't set up to catch, and you don't have enough engineers to write all the tests you're going to need. Your only chance for survival: hitch a ride with a friendly team of verification experts for this online seminar covering Testbench Automation, Reuse, and Functional Coverage. Please note that we also are offering this online seminar in video and audio only (MP3) formats.FPGA designers are needing better controllability, observability, and architectural exploration to meet the critical system performance and cost pressures. Within the Seamless co-verification environment, Xilinx designers can take advantage of the unique software and hardware programmability of the Xilinx Virtex-II Pro FPGAs, with the embedded PowerPC 405 processor. Co-Verification reduces overall design effort because it is faster than logic simulation, provides exceptional debug compared to a prototype, and enables performance analysis. As functional verification challenges continue to pressure project schedules, the need to increase productivity while efficiently managing against plan continues to grow. Questa's Unified Coverage Database and verification management capabilities integrate into existing verification processes providing the structure necessary to navigate progress through the inevitable twists and turns that might otherwise deviate a project from its plan. Advanced functional verification solutions speed the journey by automating development of the verification environment and test generation. Powerful debug capabilities combined with the industry's leading assertion library quickly clear the way of obstructions that might otherwise significantly stall progress. Complementing the best navigation system and latest in analysis and debug capabilities is the fastest verification engine available to speed your verification journey, Questa is the co-pilot to help guide you through your next verification mission. During this short presentation, you will learn more about Seamless, Mentor Graphics hardware/software co-verification solution. We will discuss the goals of co-verification and the best time to conduct it, both for hardware and software. We also look at performance analysis of software, memory, and bus characteristics.
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Advanced Debug with ModelSim Web Seminar