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PCIe VIP Workshop



Verification of IP blocks, subsystems and complete SOCs is a major challenge for the industry today. Verification teams are using multiple tools and methodologies to achieve design functionality. One very common and valuable tool is Verification IP. Mentor Graphics VIP provides comprehensive protocol test stimulus, verification planning, protocol specific functional coverage, assertions, transaction level debug are standard components of Mentor VIP. This workshop will show you how having a standard interface is a great opportunity for your team to easily deploy these advanced verification methodologies to bring up your PCIe enabled system.

Mentor VIP leverages SystemVerilog, and some knowledge of this or UVM/OVM is recommended. Many tools and techniques exist to help with this problem including languages, verification methodologies and EDA tools. The industry is standardizing on SystemVerilog to enable modern verification techniques such as assertions, constrained random and functional coverage and methodologies such as OVM and now UVM to provide an infrastructure to leverage that functionality and enable re-use across projects.

On the design side we are seeing increased use of industry standard interfaces to enable the reuse of design IP necessary to compete in the marketplace. This necessitates independent and rigorous testing of design interfaces, but also enables standard verification IP to be created that can be reused across projects. This need is why we leverage advanced verification methodologies like verification planning, constrained random and functional coverage with our VIP.

The workshop will focus on PCIe which is one of the most commonly used protocols and also one of the most complicated. Using Mentor VIP you will learn how to verify your DUT at a higher level of abstraction.

What You Will Learn

  • How Mentor VIP can help you test your design
  • Common usage scenarios of a PCIe based DUT and integration in an existing testbench
  • How to integrate a VIP to test a sample design using advanced transaction level debugging
  • How to do initial link up in a PCIe environment and exchange TLPs to verify the DUT
  • How to do error injection in a PCIe environment
  • How to collect accurate coverage data for your design and detect holes in his testing methodology


Who Should Attend

  • Design Verification Engineers and Managers
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