PowerAware Verification Hands-on Workshop
Power management has become a critical aspect of both design and verification in today's SoC designs. In addition to the demand for more functionality and longer battery life, today's SoC designs are typically manufactured at process technologies below 90nm, where static leakage current becomes the dominate source of power consumption. Verification of the techniques employed to combat static leakage current typically have been employed at the end of the design cycle where bugs are both difficult to detect and expensive to fix. This workshop presents Questa's PowerAware Simulation (PASim) solution and describes how it is being used today to verify active power management in complex SoC designs. The workshop will explain how IEEE Std 1801 UPF is used to define the power management architecture for a device early in the design cycle and when used with Questa's PASim capabilities, enables visualization and debugging of active power management techniques and its effect on design functionality.
What You Will Learn
- The UPF constructs for power domain partitioning, specifying isolation, level shifting, retention, and power state tables and how to apply them to a design
- Questa's UPF processing capabilities including both the static and dynamic assertion checks and power related report generation for maximizing debug productivity
- Questa's advanced power related simulation debug capabilities for visualizing corruption, isolation and coverage analysis
Who Should Attend
- Design Verification Engineers and Managers