Power Aware Verification Web Seminar
On-demand Web Seminar
With total power consumption of an IC now one of the major design constraints, design teams have started to adopt low power design techniques (e.g. Power Gating with/ without retention, Multi Voltage Multi Supply, Adaptive Voltage and Frequency scaling etc) in order to meet their power budgets.
The use of these low power design techniques introduces, among other things, verification challenges since new digital functionality has to be added in order to control the voltage of the power sources in order to reduce total power consumption including leakage and switching power components.
Often times, there is a software component that forms part of the overall low power design which must be verified as well. Until recently, verification of low power designs were done using adhoc practices that did not scale across projects in an organization..
In this session we will look at how new standards, verification tools and techniques can be applied to allow low power designs being verified much earlier at the RTL including the software components.
What You Will Learn
- Overview of the Low power design techniques
- Specification of low power design architecture in an SoC using IEEE 1801 UPF
- Low power bugs that could be introduced as a result of adopting Low power design techniques
- Early verification of low power designs at RTL leveraging power aware simulation tools and static checks
About the Presenter
Gabriel Chidolue is a Verification Technologist within the Design Verification Technology Division at Mentor Graphics.
He is responsible for deployment of new and emerging Verification technologies including low power verification through close collaboration with strategic partners. In this role, Gabriel works closely with customers, partners and R & D worldwide to create low power verification tools and methodologies that helps address the various verification challenges being faced by customers and partners. He has authored and co-authored papers and industry articles on low power verification.
Gabriel Chidolue holds an MSc in Concurrent Engineering in Electronic Product Design from Bournemouth University UK and B. Eng in Electrical Engineering from University of Nigeria
Who Should Attend
- Design Engineers
- Project Managers
- Engineering Managers
This web seminar is part of our Tuesday Tech Talks.
What do I need to watch and hear this web seminar?
Mentor Graphics’ web seminars are delivered using Adobe Connect. You will be able to login to the seminar room 15 minutes prior to the start time on the day of the presentation. You can hear the audio using your computer’s speakers via VoIP (Voice over IP) and background music will play prior to the beginning of the presentation.
Detailed system requirements
- Windows XP, Windows Vista, Windows 7, Windows 8
- Microsoft Internet Explorer 7, 8, 9, 10; Mozilla Firefox; Google Chrome
- Adobe® Flash® Player 10.3 or later
- 1.4GHz Intel® Pentium® 4 or faster processor and 512MB of RAM
Mac OS X, 10.5, 10.6, 10.7.4, 10.8
- Mozilla Firefox; Apple Safari; Google Chrome
- Adobe Flash Player 10.3
- 1.83GHz Intel Core™ Duo or faster processor and 512MB of RAM
- Ubuntu 10.04, 11.04; Red Hat Enterprise Linux 6; OpenSuSE 11.3
- Mozilla Firefox
- Adobe Flash Player 10.3
- Apple supported devices: iPad, iPad2, iPad3; iPhone 4 and 4 S, iPod touch (3rd generation minimum recommended)
- Apple supported OS versions summary: iOS 4.3.x, 5.x, or 6.x (5.x or higher recommended)
- Android supported devices: Samsung Galaxy Tab 2 (10.1), Samsung Galaxy Tab (10.1), ASUS Transformer, Samsung Galaxy Tab (7”) , Motorola Xoom, Motorola Xoom 2, Nexus 7
- Android supported OS versions summary: 2.2 and higher
- Android AIR Runtime required: 3.2 or higher
- Bandwidth: 512Kbps for participants, meeting attendees, and end users of Adobe Connect applications. Connection: DSL/cable (wired connection recommended) for Adobe Connect presenters, administrators, trainers, and event and meeting hosts.