Effective Processor-based SoC Verification Workshop

There are currently no dates scheduled for this event.

Overview

One of the biggest problems in SoC verification is the inability to develop production code alongside the simulator. The lack of visibility into the processor severely limits the use of firmware or even rudimentary processor-driven tests to verify your SoC hardware. You may already know how difficult and time-consuming it is to figure out what went wrong in a failing simulation. Manually slogging through log. EIS or other processor trace files, assembly listings, symbol tables, and logic simulation waveforms is slow and very inefficient. Codelink provides processor debug views for source/assembly, registers, memories, variables, etc. that are completely synchronized with the logic waveforms.

You can run Codelink during simulation, and perform live, interactive post-simulation debug. You can step forward and backward through the simulation log in a matter of seconds. Codelink non-intrusively monitors ARM, MIPS, or IBM PowerPC processors in design signoff model, RTL, or gate form instantiated in a block or chip-level simulation and requires no change to the design or processor models.

In this workshop you will learn how Codelink accelerates the diagnostic and debug phase of your SoC design.

What You Will Learn

• How to use Codelink to effectively debug your embedded processor-based SoC design
• What are the Codelink benefits for a processor-driven verification methodology
• How to setup and invoke Codelink in your Questa-based logic simulation verification environment
• Hands on experience using Codelink on an existing design