Productivity & Coverage for UVM
As SoC and ASIC designs continue growing in both size and complexity and FPGA devices now becoming SoCs themselves, design and verification teams are constantly searching for ways to increase their verification productivity and design quality to keep up with this growing challenge. There have been several methodologies introduced in the past that are aimed at addressing these challenges. Accellera’s Universal Verification Methodology (UVM), with its library created in SystemVerilog, is the first methodology that incorporates lessons learned from those previous methodologies and is supported and endorsed by all three major vendors in addition to a growing Eco-System of providers.
There is a great deal of buzz around UVM today. Engineers and managers want to understand better how it will benefit them, what effort will it take to adopt, what is available to help, how they fit it into their current environment and do they have the right people to maximize its benefits.
What You Will Learn
- How to close the loop between verification plans and verification using electronic closure to ensure you hit your market windows on schedule.
- How to reduce the volume of data within the process while still having full visibility into the progress of the project.
- How to jumpstart the debug process by analyzing results across multiple tool runs.
- How to achieve your targeted functional coverage 10x to 100x times faster
- How to ensure that each and every test sequence generated has a purpose
- How to extend coverage capability across an entire simulation server farm
- The design functions correctly with power always on
- The power management architecture is correct
- Each block/power domain can power up/down and reset/restore on power up
- The HW is generating correct control signals in the correct sequence
- The full system including HW and SW for power control is functioning correctly
- How Clock domain crossing (CDC) verification can eliminate the risk of metastability issues in silicon
- How Automatic formal checks for push-button checking find functional issues without writing a testbench or assertions
- Formal code coverage closure to prune unreachable bins from the coverage model
- Connectivity validation to exhaustively explore all modes of IP block and multi-function I/O connections
About the Presenter
Harry Foster is Chief Scientist for the Mentor Graphics Design Verification Technology Division. He holds multiple patents in verification and has co-authored seven books on verification. Harry was the 2006 recipient of the Accellera Technical Excellence Award for his contributions in developing industry standards, and was the original creator of the Accellera Open Verification Library (OVL) standard.
Who Should Attend
Verification Engineers and Managers
- 8:30 – 9:00 - Registration and Continental Breakfast
- 9:00 – 10:00 - Keynote: From Paradox to Paradise: Evolving SoC Functional Verification Capabilities, Harry Foster
From Paradox to Paradise: Evolving SoC Functional Verification Capabilities
A remarkable emergence of new advanced verification techniques, methodologies, languages and new standards has occurred in the past ten years. And recent industry studies have indicated a rapid acceleration in their adoption. This is true across all types of IC design and geographic regions. Designers and verification engineers are surprisingly open to new approaches to keep pace with the relentless rise in design density.
Yet for many projects, the process of evolving a team's functional verification capabilities presents a paradox. That is, some projects are unable to quantify the effectiveness of these new processes they put in place—or identify opportunities for process improvement—due to the lack of process measurements. As the saying goes, if you can’t measure it, you can’t improve it.
This presentation discusses techniques for evolving your SoC functional verification capabilities, from paradox to paradise, with the introduction of metrics-driven processes. A full set of solutions for managing, analyzing, and automating metrics-driven processes will be described.
- 10:00 – 11:30 - Effective Planning with UVM
Effective Verification Planning with UVM
As the saying goes, “if you fail to plan, you plan to fail.” The same is true of a verification project, where establishing a verification plan up-front is critical to your overall success. Starting with requirements, a verification team must be able to create an environment aimed at verifying that the design meets all of the requirements accurately. That involves designing stimulus, monitoring behavior and recording results, as well as managing the resulting data, using proper tools and techniques to turn those data into useful information, and closing the loop to correlate that information against the original requirements.
This 90-minute session will begin with a discussion of Verification Planning and Management, which will show how to approach the verification problem in a systematic way to create a plan of attack to ensure that the team is focused on the right things and that everyone can work together to achieve their verification goals. We will include an overview of ReqTracer, our requirements tracing tool, which will enable you to map individual design requirements to aspects of your verification plan, ensuring that you have verification infrastructure in place to verify all requirements. We will then discuss UVM Express, which allows designers and verification teams to begin adoption of UVM by focusing on the most critical aspects of a verification environment, using standard UVM verification components and a small amount of user code, without having to be an expert in object-oriented programming.
From there, we will discuss the Verification Management features of Questa, which allow you to collect, categorize, analyze and triage your verification results to ensure that your verification coverage goals have been met, and that your verification infrastructure, from your UVM environment to your regression server farm, is being used to its maximum efficiency to achieve verification closure, as defined by the initial requirements.
- 11:30 – 12:15 - Lunch
- 12:15 – 1:45 - Building, Running, Understanding your UVM Environment
Building, Running and Understanding your UVM Environment
Once you have done your planning for verification, it is time to build it and run it. This 90 minute session will focus on key concepts and tools available to help construct, simulate and debug your UVM testbench. It will incorporate things that you have learned from the plan and how to implement them along with techniques and tools that can both make the construction and debug easier but also get maximum reuse and efficiency from UVM.
During the construction phase, the focus is on creating and reusing components, evaluating availability for standard protocol components such as AMBA, USB, PCIe, constructing your test infrastructure and how you want measure and evaluate results. As you are building your testbench and connecting it to your DUT, you will need a complete debug environment that is both SystemVerilog class aware and UVM aware in addition to RTL to efficiently debug your dynamic testbench and your DUT together. Additionally there may be a need to bring in IP and other capabilities from languages such as SystemC to enable complete flows and methodologies with UVM.
During this session we will introduce tools for creation - UVM rule/lint checking, UVM templates to obtain correct-by-constructions results, register RTL and testbench creation, and graphical visualization of the UVM testbench structure; tools for debug - Questa Debug environment has special windows and features dedicated to UVM and SystemVerilog class concepts that give users full debug control and visibility; and an introduction to Questa VIP family for UVM which are built natively from UVM and include powerful debug features enabled in Questa for verification plan tracking and transaction analysis. As a wrap up, this session will discuss UVM Connect, the new open library for connecting together languages and environments such as SystemC to UVM/SystemVerilog using standard TLM 1.0 or TM 2.0.
- 1:45 – 3:15 - Achieving Coverage Closure Faster with the UVM Methodology
Achieving Coverage Closure Faster with the UVM Methodology
Recent industry surveys show that two-thirds of new design projects fall behind schedule due to verification. In addition, 70% of these designs fail at least once after verification is completed. With over half of these failures attributable to logic and functional errors, it makes sense that more verification teams are turning to the UVM methodology to address their coverage closure challenges.
With Questa's UVM-based functional verification platform, achieving coverage closure means much more than just generating stimulus and hoping for coverage results. Questa eases UVM testbench programming by automatically generating coverage models. Questa's Verification Management reduces the time needed to manage regression testing and merge coverage results from hours to minutes. And Questa inFact intelligently generates UVM stimulus to ensure that high test quantity does not come at the expense of high test quality.
Attend this session to learn how Questa can help you can gain 10X to 100X in UVM-based verification productivity by:
- Automatically generating SystemVerilog covergroups and Clock Domain Crossing coverage models
- Intelligently generating UVM stimulus that achieves target coverage closure faster, and increases overall coverage
- Verifying internal design state coverage with Formal Verification
- Improving productivity by tying this all together with Questa's UVM-based functional verification platform
Injecting Automation into Verification – Code Coverage
This webinar provides an introduction to the use of code coverage in today’s HDL design and verification flows.
This video provides an overview of Mentor Graphic's ModelSim software. You will learn the essential skills needed to create a simulation environment and what tools are available to quickly debug the...