Debug Productivity with Questa: Introduction to advanced debug features in Questa for SystemVerilog class-based TB, OVM/UVM, and hard to find problems in RTL
On-demand Web Seminar
No one argues that today’s designs are rapidly growing in both size and complexity. Often IP is brought together from multiple sources (both internal and external), and can involve multiple design languages. To increase productivity and quality, verification engineers are also adopting advanced techniques and methodologies such as ABV(Assertion Based Verification)and OVM/UVM (Open/Universal Verification Methodology) and using languages such as SystemC and SystemVerilog. This variation and complexity in the verification environment demands new automation and capabilities for effective debug.
With native support of VHDL, Verilog, SystemVerilog and SystemC, Questa has a rich set of debug technology and functionality to help diagnose problems and find bugs fast. This webinar will introduce the advanced debug capabilities available in Questa for class-based debug of OOP environments with SystemVerilog, OVM, UVM and SystemC, Assertion debug with SVA or PSL and advanced traditional RTL debug with process debug, waveform compare, transaction-level debug, source code tracing, schematic view, causality tracing, X-trace, and other productivity features.
What You Will Learn
An introduction to:
- How advanced debug capabilities can help you rapidly uncover design issues
- How Questa's assertion debug capabilities can help you understand and debug your assertions
- How Questa's advanced SystemVerilog debug capabilities can you help you debug your OOP code using familiar hardware debug techniques
About the Presenter
A background in Digital Signal Processing and more then 15 years of EDA experience. I entered the Electronic Design Automation (EDA) in 1990 as an application engineer and continued my career to consultancy. Working in international teams I have then become a leading member in EDA product development for European and American companies. As part of the InnoFour team I am dedicated to deliver productive engineering and electronic development solutions to our customers via the best in class software, support and consultancy for tomorrows complex designs.
Who Should Attend
- Design and Verification Engineers
What do I need to watch and hear this web seminar?
Mentor Graphics’ web seminars are delivered using Adobe Connect. You will be able to login to the seminar room 15 minutes prior to the start time on the day of the presentation. You can hear the audio using your computer’s speakers via VoIP (Voice over IP) and background music will play prior to the beginning of the presentation.
Detailed system requirements
- Windows XP, Windows Vista, Windows 7, Windows 8
- Microsoft Internet Explorer 7, 8, 9, 10; Mozilla Firefox; Google Chrome
- Adobe® Flash® Player 10.3 or later
- 1.4GHz Intel® Pentium® 4 or faster processor and 512MB of RAM
Mac OS X, 10.5, 10.6, 10.7.4, 10.8
- Mozilla Firefox; Apple Safari; Google Chrome
- Adobe Flash Player 10.3
- 1.83GHz Intel Core™ Duo or faster processor and 512MB of RAM
- Ubuntu 10.04, 11.04; Red Hat Enterprise Linux 6; OpenSuSE 11.3
- Mozilla Firefox
- Adobe Flash Player 10.3
- Apple supported devices: iPad, iPad2, iPad3; iPhone 4 and 4 S, iPod touch (3rd generation minimum recommended)
- Apple supported OS versions summary: iOS 4.3.x, 5.x, or 6.x (5.x or higher recommended)
- Android supported devices: Samsung Galaxy Tab 2 (10.1), Samsung Galaxy Tab (10.1), ASUS Transformer, Samsung Galaxy Tab (7”) , Motorola Xoom, Motorola Xoom 2, Nexus 7
- Android supported OS versions summary: 2.2 and higher
- Android AIR Runtime required: 3.2 or higher
- Bandwidth: 512Kbps for participants, meeting attendees, and end users of Adobe Connect applications. Connection: DSL/cable (wired connection recommended) for Adobe Connect presenters, administrators, trainers, and event and meeting hosts.
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