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ModelSim & Questa: Smarter Simulation

Overview

Today’s FPGAs and ASICs are ever increasing in density and complexity and the result of this is that the design verification is growing at an exponential rate. Engineers have tried to counter this by using faster and faster computers and multi-processing but this is not enough. The tide has now turned and engineers and their management now see that simulating faster will no longer be enough, we need to simulate and verify smarter. This event will show the results of the many hundreds of man-years of effort by the Mentor developers to make smarter simulation easier.

This event is aimed at both non-users and existing users.

It will introduce non-users to the basic and more advanced debugging and verification capabilities within ModelSim and Questa and give tip and tricks on how best to use these within a design and verification flow.

Existing users who already see the value of our advanced solution may are often unfamiliar with many of the latest ever-evolving capabilities within their tools, so this event will also raise the capabilities of these to allow them to become more efficient, time-effective and ‚smarter‘ in debugging and verification.

What You Will Learn

You will learn some of the essential modern techniques for FPGA and ASIC design and verification and how to make use of the basic and more advanced capabilities of Mentor Graphics’‘ best-in-class solutions in terms of simulation and verification.

  • Non-users will learn the possibilities to improve their existing flows by changing to ModelSim or Questa.
  • Existing users will be able to further speed up their existing flows by making use of of our latest enhancements to these tools.

Who Should Attend

  • FPGA & ASIC designers
  • Semiconductor companies
  • Semiconductor developers/Researchers
  • Responsible Development Managers

Products Covered

 
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