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Step-up Your Verification Efficiency

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Overview

Join us for a free in person seminar to learn how to use the latest techniques to further improve your FPGA verification processes.

It is 2014, Altera is “Delivering the unimaginable” and Xilinx is delivering “All Programmable SoCs” to design centers. It is clear that the SoC has become more accessible to a broader market, it is also clear the FPGA vendors have staked out a solid technology roadmap.  Mentor Graphics has been engaged in the design verification for many decades and has mature verification flows that provide design teams valuable productivity for the SoC, Midrange and low-cost FPGA market. 

Many successful companies have already adopted the SoC verification automation flow in the FPGA domain and sell high quality products.  However there are still many teams that are unable to fulfill the growing verification gap and end up deploying the same in-lab design bring up techniques used for lower capacity FPGAs regardless of the design verification challenge.

What You Will Learn

Have you already heard of the 3-step Injecting Verification Automation proposal? The 3-step process, providing coverage, improved debug and improved throughput  has inspired many teams to improve their own productivity and smooth their in-lab system bring up efforts.  We will show you a practical example of how using the 3-step process will improve your verification process and get out of the lab with a higher quality product.   The seminar will highlight how your team can adopt the 3-step proposal incrementally or all at once, so you can improve the return on investment on existing simulation tools. With this practical example you will gain insight on the latest techniques to further improve your FPGA verification processes.

Do you think deployment of new verification technology is beyond your reach? Has anyone in your team asked about how to improve development productivity, schedule predictability or simply finding it too concerning to be debugging the same types of problems in the FPGA Hardware Lab over and over again? Do you think the tool costs and engineering costs are too high for you to invest in new ideas?  We understand the FPGA design community has many challenges. This is why we invest in providing solutions that provide value for ever day tasks,  let us show you the results of our focus on teaching your team how to deploy these verification solutions.  In this seminar we will provide perspectives into the market forces that are driving FPGA development environments, show you a common and practical example of an improved verification process and show you the resources to deploy.  You can effectively break the FPGA design verification barrier. 

About the Presenter

Presenter Image Joe Rodriguez

Joe Rodriguez is a FPGA Market Development for Design Verification Technology (DVT) division at Mentor Graphics. Prior to this role Joe spent 2 years as Technical Marketing Manager for the Emulation Division (MED) at Mentor Graphics. Joe was also the Technical Marketing Manager in DVT at Mentor Graphics for 12 years. A result of this Joe has been involved in the definition and creation of many aspects of the Mentor Graphics verification solutions. Solutions like power aware simulation, debug and performance flows, including US patents for simulation event reduction.

Prior to Mentor Graphics, Joe spent 5 years as a field application engineer for Quickturn Design Systems successfully deploying many large FGPA based emulation projects. Joe also spent 6 years at Logic Automation as a Modeling Engineer and Support Manager. Joe has 7 years experience as a diagnostic engineer at Floating Point System and holds a Bachelor of Science in electrical engineering.

Who Should Attend

  • FPGA design and verification engineers
  • Engineering managers dealing with FPGA verification
 
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