SystemVerilog Assertions Workshop
There are currently no dates scheduled for this event.
Overview
As design size and complexity increases the need for automatic simulation checking also increases. Assertions provide a mechanism for ensuring design intent as well as measuring verification test bench effectiveness.
In this workshop you will write assertions to verify design behavior as described in a truth table.
Seating is very limited to maximize your learning experience, so submit your interest immediately to request your spot.
What You Will Learn
This seminar covers the structure and use of assertion libraries, OVL/QVL, as well as the SVA assertion language. Topics include assertion library components, assertion binding, SVA sequence and property constructs and assertion coverage. Class exercises include SVA assertion creation from design requirements specification.
About the Presenter
Bob Oden
Bob Oden is a Sr. Application Engineer at Mentor Graphics. He joined Mentor in 2006 with fifteen years of ASIC and FPGA design and verification experience. Companies he has worked for include AMCC, Nortel, Xerox, and Harris. He holds three U.S. patents in the area of telecommunications design. His responsibilities at Mentor include mentoring, training, and consulting in advanced verification methodologies and technologies. Bob lives in Raleigh, North Carolina, with his wife Tami and their three children.
Who Should Attend
- Design Engineers
- Verification Engineers
- Project Engineering Leads
Products Covered
Web Series: SystemVerilog
Each workshop may be taken independently based on subject matter interest. Together, the workshops offer a broader view of these complementary technologies and how they integrate into your existing verification flow.