SystemVerilog HW Verification Language Workshop
There are currently no dates scheduled for this event.
Overview
SystemVerilog, IEEE-1800, is becoming the dominant language for the creation of functional verification environments.
This powerful hardware verification language and hardware design language includes constructs for dynamic data generation, structures, classes, constrained random generation, semaphores, mailboxes, virtual interfaces and more.
Seating is very limited to maximize your learning experience, so submit your interest immediately to request your spot.
What You Will Learn
In the exercises, you will modify a transaction level generator and driver using System Verilog interfaces. This stimulus generator can be included in any current SystemVerilog, Verilog or VHDL environment.
About the Presenter
Bob Oden
Bob Oden is a Sr. Application Engineer at Mentor Graphics. He joined Mentor in 2006 with fifteen years of ASIC and FPGA design and verification experience. Companies he has worked for include AMCC, Nortel, Xerox, and Harris. He holds three U.S. patents in the area of telecommunications design. His responsibilities at Mentor include mentoring, training, and consulting in advanced verification methodologies and technologies. Bob lives in Raleigh, North Carolina, with his wife Tami and their three children.
Who Should Attend
- Design Engineers
- Verification Engineers
- Project Engineering leads
Products Covered
Web Series: SystemVerilog
Each workshop may be taken independently based on subject matter interest. Together, the workshops offer a broader view of these complementary technologies and how they integrate into your existing verification flow.
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