Transforming Verification Seminar
The challenges of verification continue growing exponentially. Through advances in technology and methodology, verification productivity has improved dramatically over the past decade. Yet, the continuing growth in the size of verification teams and the amount of project time dedicated to verification indicate the need for greater advances in productivity. As we enter the era of SoCs, verification complexity will be driven by increased design complexity of multiple cores running many applications to deliver on-demand content in consumer devices such as tablets and smartphones.
It is clear that verification must be transformed in order to deliver the productivity that will enable the next generation of multi-core SoC consumer electronics. Innovative technologies that deliver 10-100x advances in verification are required. As the impact of software in electronic systems grows, verification solutions must expand to enable co-verification with advanced verification technology. Comprehensive solutions and methodology will integrate these innovative tools and enable real-time progress tracking, trend analysis and increased automation and efficiency of the verification process.
If you need to transform your verification processes to dramatically boost productivity, radically decrease time-to-coverage, and more effectively and efficiently manage your verification processes, then the Transforming Verification seminar is for you!
About the Presenter
Harry Foster is Chief Scientist for the Mentor Graphics Design Verification Technology Division. He holds multiple patents in verification and has co-authored seven books on verification. Harry was the 2006 recipient of the Accellera Technical Excellence Award for his contributions in developing industry standards, and was the original creator of the Accellera Open Verification Library (OVL) standard.
- 9:00 – 9:50 - Keynote Harry Foster
From Volume to Velocity
There has been a remarkable acceleration in the adoption of advanced verification methodologies, languages and new standards. This is true across all types of IC design and geographic regions. Designers and verification engineers are surprisingly open to new approaches to keep pace with the relentless rise in design density. They are looking beyond simply increasing the volume of verification to instead using advanced techniques to improve the velocity of verification.
The result is design teams have not lost ground on meeting schedule goals or first-pass silicon success even as design complexity has grown. Now the focus is shifting to appreciably improving those metrics while shrinking verification costs.
Harry Foster, will discuss the state of verification past, present and future. After examining the results from a leading verification survey, he’ll look at how advanced techniques are taking hold in mainstream design. Harry will then offer his insights on where verification needs to evolve to ensure continued improvement.
- 10:00 – 10:50 - Verification Management and Planning
Verification Management and Planning
When verification is not under control, project schedules slip, quality is jeopardized and the risk of re-spins soars. What’s required is a common platform and environment that provides all parties – system architects, software engineers, designers and verification specialists – with real-time visibility into the project. And it’s not just to the verification plan, but also to the specifications and the design, both of which change over time.
There are three dimensions to any IC design project: the process, the tools and the data. Mentor Graphics Questa® Verification Management offers a comprehensive approach to verification management that handles them all. With the flexibility which allows enabling technologies to be deployed either alongside current legacy verification environments, incrementally replace them in a modular fashion or benefit from the power and integration of the complete solution.
Verification management should be based around a structured process but also requires the tools to allow this process to be automated. Given the rise in design complexity, it’s no surprise that data management is increasingly the foundation of any verification management activities. This session will cover:
- How to close the loop between verification plans and verification using electronic closure to ensure you hit your market windows on schedule.
- How to manage priorities, risk and keep resources on track.
- How to reduce the volume of data within the process while still having full visibility into the progress of the project.
- How to jumpstart the debug process by analyzing results across multiple tool runs.
- How reduce maintenance, improve automation and ensure your efforts are focused on verification and not environment infrastructure.
- 11:00 – 11:50 - Accelerating Coverage Closure
Accelerating Coverage Closure
Achieving functional coverage closure in today’s complex designs is challenging and time consuming. It is common for a verification team to spend a disproportionate amount of time attempting to achieve the last 20% of functional coverage, by identifying corner cases manually, struggling to create overly complex constraints, and often times resorting to writing lengthy directed tests to target these cases.
Mentor Graphics has a proven methodology to accelerate functional coverage closure, freeing up resources to achieve more verification. Questa’s Intelligent Testbench Automation solution generates stimulus according to the user’s functional coverage goals, eliminating redundant stimulus and efficiently targeting corner cases. The result is 10x to 100x faster functional coverage closure. This session will discuss:
- How to achieve your targeted functional coverage 10x to 100x times faster
- How to ensure that each and every test sequence generated has a purpose
- How to achieve the most verification per cycle of simulation
- How to extend this capability across an entire simulation server farm
- How to do this while reusing 95% or more of your existing verification IP
- 11:50 - 12:40 - Lunch
- 12:40 – 1:30 - Verifying Power Managed SoCs and ASICs
Verifying Power Managed SoCs and ASICs
Power management is no longer an option. Studies show that over 50% of the market is already incorporating power management into their SOC and ASIC designs. For designs that push the envelope in terms of small geometries, the number of companies incorporating power management quickly rises to over 70%. Mentor has been very active in specifying power management architecture and functionality in terms of verification requirements and solutions, including the delivery of the technology, expertise and leadership which resulted in the IEEE’s Unified Power Format(UPF). Today, our low power solutions provide comprehensive verification of power managed designs including leading-edge support for UPF2.0.
Verification engineers, managers, and directors, dealing with low power management and control, now have a whole new set of multi-dimensional verification questions which need to be answered including,
Have I taken the proper steps to verify that:
- The design functions correctly with power always on
- The power management architecture is correct
- Each block/power domain can power up/down and reset/restore on power up
- All interfaces are correctly isolated and level shifted
- All transitions are covered and behave correctly with power control
- The HW is generating correct control signals in the correct sequence
- The SW Power Control interfaces with HW is correctly
- The full system including HW and SW for power control is functioning correctly
If you are actively managing and controlling power within your design, this session will show you how Questa’s low power solutions can help you comprehensively cover these challenges.
- 1:30 – 2:20 - 5 easy ways to adopt ultra-high performance formal tools
5 easy ways to adopt ultra-high performance formal tools
The adoption of formal verification technology has traditionally been encumbered by performance, capacity and ease of use issues.
With the Questa Formal Based Technologies, complete SoC designs, greater than 150M gates in size, can now be analyzed in a single step. Tens of thousands of assertions for multi-million gate design blocks can now be proven in a matter of hours. Huge strides have been made in advancing the usability of the formal tools, with the development of new features and refinement of methodologies, so that this groundbreaking power has been brought to a whole new level of automation.
In this session, we discuss the top five applications offered with the Questa Formal Based Technologies that are being used in the industry today:
- Clock domain crossing (CDC) verification to eliminate the risk of metastability issues in silicon
- Automatic formal checks for push-button checking to find functional issues without writing a testbench or assertions
- Formal code coverage closure to prune unreachable bins from the coverage model
- Static X-propagation verification to verify that X-optimism is not masking design bugs
- Connectivity validation to exhaustively explore all modes of IP block and multi-function I/O connections
Injecting Automation into Verification – Improved Throughput
Improving productivity has many forms, simulation performance, debug effectiveness, even writing test scenarios. We will highlight high value techniques for improving throughput.
Injecting Automation into Verification - Assertions
What we will show in this webinar is how we can leverage Assertions, including the pre-defined, pre-tested OVL libraries, to automate the verification process further. What we will also show is the way...
Injecting Automation into Verification – Code Coverage
This webinar provides an introduction to the use of code coverage in today’s HDL design and verification flows.