UVM Debug Workshop

Hands-on Workshop
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There are currently no dates scheduled for this event.

Overview

UVM has become the de-facto standard for building verification environments that are needed for today’s complex designs. In this "hands-on" workshop, you will be exposed to the techniques and skills that will enable you to confidently and quickly navigate through your verification environment. The unique debug capabilities in the Questa Verification Platform will make it easier and faster to debug your UVM testbench, so that you can get on with the real task of verifying your design.

Who Should Attend

  • Design and Verification Engineers and Managers

What You Will Learn

  • How to debug UVM-based testbenches using Questa
  • SystemVerilog class-based debug features in Questa
  • UVM debug utilities
  • Transaction-based debug

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