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Verification Academy Live!

Join us for this special Verification Academy Live session! This comprehensive event delivers practical “new school” verification sessions that will discuss technologies and techniques you can start adopting to increase your verification productivity.

Austin Agenda Santa Clara Agenda


Efficient Verification

presented by Rajesh Goel, Qualcomm
September 18


Verification at ARM: Archaeology and Future Directions

presented by Alan Hunter, ARM
September 11



Presentations will discuss the very latest for coverage closure, stimulus generation, fast and efficient VIP,  debug techniques that will help you answer the age old question “am I done yet”, details for designing an efficient UVM Testbench and new approaches for Software Driven Verification.

As a featured keynote, Harry Foster will discuss the latest from the 2014 Verification survey, introducing today’s trends and challenges in SoC design and verification as he outlines a path for navigating to success.

Featured Presentations

Austin, TX - Sept 11


Verification at ARM: Archaeology and Future Directions
presented by Alan Hunter

This session will present ARM's verification journey over the last 15 years. Will discuss where they started, technologies and methodologies that have been adopted along the way (the good and the bad) what worked and where they are heading tomorrow for maximizing productivity.

Santa Clara, CA - Sept 18


Efficient Verification
presented by Rajesh Goel

Design sizes are growing faster than ever before and verification complexity is growing exponentially. Time to market has been shrinking, shortening the project cycles. We cannot scale verification resources exponentially to meet these demands, and cannot run every available test in simulation for each design change. Verification needs to get smarter. We will have to invest time in improving the effectiveness of every simulation cycle for verification. In this challenging market quality is very important and so is time to market. There is tremendous pressure to get product out faster and this is reducing the time between first tapeout and commercialization. Our products are a combination of SW & HW, and for successful commercialization the stability of system (SW+HW) is critical. To enable this early SW+HW verification we rely on different platforms which can enable SW driven verification pre-silicon. In this talk we will review how to get efficient and smarter about verification of HW with SW for functional, power, performance, and beyond. Backdrop for this talk is GPU verification in Qualcomm and focus is simulation acceleration.

About the Presenters

Presenter Image Harry Foster

Harry Foster is Chief Scientist for the Mentor Graphics Design Verification Technology Division. He holds multiple patents in verification and has co-authored seven books on verification. Harry was the 2006 recipient of the Accellera Technical Excellence Award for his contributions in developing industry standards, and was the original creator of the Accellera Open Verification Library (OVL) standard.

Presenter Image Alan Hunter

Alan has been with ARM for over 15 years.  He is currently based in Austin working on next generation CPU IP. Interests include formal methods, partner deliverables, process automation, TBA, test planning, coffee and brewing.  Been an active formal methods guy for 17 years.

Presenter Image Rajesh Goel

Rajesh Goel is Director Engineering at Qualcomm where he is responsible for design verification of Graphics hardware. He founded design verification team for multi-media IPs within Qualcomm where he was leading verification of audio, video, camera, graphics, display, and entire sub-system. Prior to that he was verification lead for Qualcomm SoCs for mobile devices. Before Qualcomm he worked at Spike Technologies in design services verifying complex designs for Cisco, Fujitsu, Intel, and many start-ups. With 18 years of design verification experience he has not only verified designs to highest quality but always worked towards process and methodology improvements to enhance quality of designs and increase verification resource efficiency. Rajesh completed his degree in engineering from Delhi College of Engineering in 1996.

Who Should Attend

  • Verification engineers and managers
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